Abstract: Methods for improving the net remnant polarization of a polymer memory cell are disclosed. In one embodiment, the polymer material is heated above the Curie temperature of the polymer material, and the domains of the polymer material are aligned with an externally applied electric field.

Abstract: The effects of a self-erase phenomenon when accessing imprinted ferroelectric memory cells that have non-conductive electrode interfaces that reduce remnant polarization and decrease signal margin are eliminated. A self-erase control pulse asserted after an access pulse is utilized. The self-erase control pulse has a magnitude sufficient to offset a remnant charge on the non-conductive electrode interfaces after the removal of the access pulse.

Abstract: A combination wafer is manufactured by (i) forming a plurality of alternating dielectric and metal layers, (ii) forming a guard ring trench in the layers, (iii) forming a guard ring layer in the guard ring trench, and then repeating (i), (ii) with a slightly wider guard ring trench, and (iii). A number of layers are thus simultaneously etched and lined with a guard ring layer, but the number of layers is not so large so as to cause lithographic problems that may occur when a deep, narrow guard ring trench is formed. An upper one of the layers that are patterned is always made of silicon dioxide, which includes less carbon than lower polymer layers and allows for a carbon mask to be formed and be easily removed. The slightly wider guard ring trench each time the process is repeated overcomes lithographic alignment problems that may occur when the guard ring trenches are exactly the same size. Subsequent guard ring layers are partially formed on one another, and provide a moisture seal.

Abstract: According to one aspect of the invention, a memory array and a method of constructing a memory array are provided. An insulating layer is formed on a semiconductor substrate. A first metal stack is then formed on the insulating layer. The first metal stack is etched to form first metal lines. A polymeric layer is formed over the first metal lines and the insulating layer. The polymeric layer has a surface with a plurality of roughness formations. A second metal stack is formed on the polymeric layer with an interface layer, which is thicker than the heights of the roughness formations. Then the second metal stack is etched to form second metal lines. Memory cells are formed wherever a second metal line extends over a first metal line.

Abstract: An embodiment of the invention provides an on-chip heating system to both initially anneal and revive cycle-fatigued polymer ferroelectric materials utilized in memory devices. By heating the polymer ferroelectric material above its Curie temperature, the polymer ferroelectric material can crystallize as it cools. As such, the ferroelectric properties of the polymer are enhanced and/or restored.

Abstract: According to one aspect of the invention, a memory array and a method of constructing a memory array are provided. An insulating layer is formed on a semiconductor substrate. A first metal stack is then formed on the insulating layer. The first metal stack is etched to form first metal lines. A polymeric layer is formed over the first metal lines and the insulating layer. The polymeric layer has a surface with a plurality of roughness formations. A second metal stack is formed on the polymeric layer with an interface layer, which is thicker than the heights of the roughness formations. Then the second metal stack is etched to form second metal lines. Memory cells are formed wherever a second metal line extends over a first metal line.

Abstract: The effects of a self-erase phenomenon when accessing imprinted ferroelectric memory cells that have non-conductive electrode interfaces that reduce remnant polarization and decrease signal margin are eliminated. A self-erase control pulse asserted after an access pulse is utilized. The self-erase control pulse has a magnitude sufficient to offset a remnant charge on the non-conductive electrode interfaces after the removal of the access pulse.

Abstract: An electrode layer for a polymer memory may be implanted to increase the number of defects in the material. As a result, that same material may be utilized for the upper and lower electrodes. In particular, defects may be introduced into a TiOx layer within the electrode to match the work functions of the upper and lower electrodes.

Abstract: Methods of depositing various metal layers adjacent to a ferroelectric polymer layer are disclosed. In one embodiment, a collimator may be used during a sputtering process to filter out charged particles from the material that may be deposited as a metal layer. In various embodiments, a metal layer may contain at least one of an intermetallic layer, an amorphous intermetallic layer, and an amorphized intermetallic layer.

Abstract: Methods of depositing various metal layers adjacent to a ferroelectric polymer layer are disclosed. In one embodiment, a collimator may be used during a sputtering process to filter out charged particles from the material that may be deposited as a metal layer. In various embodiments, a metal layer may contain at least one of an intermetallic layer, an amorphous intermetallic layer, and an amorphized intermetallic layer.

Abstract: An embodiment of the invention provides an on-chip heating system to both initially anneal and revive cycle-fatigued polymer ferroelectric materials utilized in memory devices. By heating the polymer ferroelectric material above its Curie temperature, the polymer ferroelectric material can crystallize as it cools. As such, the ferroelectric properties of the polymer are enhanced and/or restored.

Abstract: A combination wafer is manufactured by (i) forming a plurality of alternating dielectric and metal layers, (ii) forming a guard ring trench in the layers, (iii) forming a guard ring layer in the guard ring trench, and then repeating (i), (ii) with a slightly wider guard ring trench, and (iii). A number of layers are thus simultaneously etched and lined with a guard ring layer, but the number of layers is not so large so as to cause lithographic problems that may occur when a deep, narrow guard ring trench is formed. An upper one of the layers that are patterned is always made of silicon dioxide, which includes less carbon than lower polymer layers and allows for a carbon mask to be formed and be easily removed. The slightly wider guard ring trench each time the process is repeated overcomes lithographic alignment problems that may occur when the guard ring trenches are exactly the same size. Subsequent guard ring layers are partially formed on one another, and provide a moisture seal.

Abstract: Methods of depositing various metal layers adjacent to a ferroelectric polymer layer are disclosed. In one embodiment, a collimator may be used during a sputtering process to filter out charged particles from the material that may be deposited as a metal layer. In various embodiments, a metal layer may contain at least one of an intermetallic layer, an amorphous intermetallic layer, and an amorphized intermetallic layer.

Abstract: By using a plurality of relatively thin stacked diffusion layers interposed between a conductive line and a polymer layer, the diffusion of contaminates into a polymer layer from the conductive line may be reduced. This may reduce part failure during fatigue or disturb testing, for example, in ferroelectric polymer memories.

Abstract: An electrode layer for a polymer memory may be implanted to increase the number of defects in the material. As a result, that same material may be utilized for the upper and lower electrodes. In particular, defects may be introduced into a TiOx layer within the electrode to match the work functions of the upper and lower electrodes.

Abstract: Methods for improving the net remnant polarization of a polymer memory cell are disclosed. In one embodiment, the polymer material is heated above the Curie temperature of the polymer material, and the domains of the polymer material are aligned with an externally applied electric field.

Abstract: According to one aspect of the invention, a memory array and a method of constructing a memory array are provided. An insulating layer is formed on a semiconductor substrate. A first metal stack is then formed on the insulating layer. The first metal stack is etched to form first metal lines. A polymeric layer is formed over the first metal lines and the insulating layer. The polymeric layer has a surface with a plurality of roughness formations. A second metal stack is formed on the polymeric layer with an interface layer, which is thicker than the heights of the roughness formations. Then the second metal stack is etched to form second metal lines. Memory cells are formed wherever a second metal line extends over a first metal line.

Abstract: A combination wafer is manufactured by (i) forming a plurality of alternating dielectric and metal layers, (ii) forming a guard ring trench in the layers, (iii) forming a guard ring layer in the guard ring trench, and then repeating (i), (ii) with a slightly wider guard ring trench, and (iii). A number of layers are thus simultaneously etched and lined with a guard ring layer, but the number of layers is not so large so as to cause lithographic problems that may occur when a deep, narrow guard ring trench is formed. An upper one of the layers that are patterned is always made of silicon dioxide, which includes less carbon than lower polymer layers and allows for a carbon mask to be formed and be easily removed. The slightly wider guard ring trench each time the process is repeated overcomes lithographic alignment problems that may occur when the guard ring trenches are exactly the same size. Subsequent guard ring layers are partially formed on one another, and provide a moisture seal.

Abstract: According to one aspect of the invention, a memory array and a method of constructing a memory array are provided. An insulating layer is formed on a semiconductor substrate. A first metal stack is then formed on the insulating layer. The first metal stack is etched to form first metal lines. A polymeric layer is formed over the first metal lines and the insulating layer. The polymeric layer has a surface with a plurality of roughness formations. A second metal stack is formed on the polymeric layer with an interface layer, which is thicker than the heights of the roughness formations. Then the second metal stack is etched to form second metal lines. Memory cells are formed wherever a second metal line extends over a first metal line.

Abstract: A combination wafer is manufactured by (i) forming a plurality of alternating dielectric and metal layers, (ii) forming a guard ring trench in the layers, (iii) forming a guard ring layer in the guard ring trench, and then repeating (i), (ii) with a slightly wider guard ring trench, and (iii). A number of layers are thus simultaneously etched and lined with a guard ring layer, but the number of layers is not so large so as to cause lithographic problems that may occur when a deep, narrow guard ring trench is formed. An upper one of the layers that are patterned is always made of silicon dioxide, which includes less carbon than lower polymer layers and allows for a carbon mask to be formed and be easily removed. The slightly wider guard ring trench each time the process is repeated overcomes lithographic alignment problems that may occur when the guard ring trenches are exactly the same size. Subsequent guard ring layers are partially formed on one another, and provide a moisture seal.