Patents by Inventor Hitohisa Ono

Hitohisa Ono has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9237283
    Abstract: In a manufacturing method of a solid-state image pickup device according to an embodiment, a transfer gate electrode is formed in a predetermined position on an upper surface of a first conductive semiconductor area, through a gate insulating film. A second conductive charge storage area is formed in an area adjacent to the transfer gate electrode in the first conductive semiconductor area. A sidewall is formed on a side surface of the transfer gate electrode. An insulating film is formed to extend from a circumference surface of the sidewall on a side of the charge storage area to a position partially covering the upper part of the charge storage area. A first conductive charge storage layer is formed in the charge storage area by implanting first conductive impurities from above, into the charge storage area which is partially covered with the insulating film.
    Type: Grant
    Filed: July 25, 2014
    Date of Patent: January 12, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsushi Ohta, Hitohisa Ono
  • Publication number: 20140333807
    Abstract: In a manufacturing method of a solid-state image pickup device according to an embodiment, a transfer gate electrode is formed in a predetermined position on an upper surface of a first conductive semiconductor area, through a gate insulating film. A second conductive charge storage area is formed in an area adjacent to the transfer gate electrode in the first conductive semiconductor area. A sidewall is formed on a side surface of the transfer gate electrode. An insulating film is formed to extend from a circumference surface of the sidewall on a side of the charge storage area to a position partially covering the upper part of the charge storage area. A first conductive charge storage layer is formed in the charge storage area by implanting first conductive impurities from above, into the charge storage area which is partially covered with the insulating film.
    Type: Application
    Filed: July 25, 2014
    Publication date: November 13, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Atsushi OHTA, Hitohisa ONO
  • Patent number: 8803204
    Abstract: In a manufacturing method of a solid-state image pickup device according to an embodiment, a transfer gate electrode is formed in a predetermined position on an upper surface of a first conductive semiconductor area, through a gate insulating film. A second conductive charge storage area is formed in an area adjacent to the transfer gate electrode in the first conductive semiconductor area. A sidewall is formed on a side surface of the transfer gate electrode. An insulating film is formed to extend from a circumference surface of the sidewall on a side of the charge storage area to a position partially covering the upper part of the charge storage area. A first conductive charge storage layer is formed in the charge storage area by implanting first conductive impurities from above, into the charge storage area which is partially covered with the insulating film.
    Type: Grant
    Filed: May 17, 2013
    Date of Patent: August 12, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsushi Ohta, Hitohisa Ono
  • Publication number: 20140217475
    Abstract: In a manufacturing method of a solid-state image pickup device according to an embodiment, a transfer gate electrode is formed in a predetermined position on an upper surface of a first conductive semiconductor area, through a gate insulating film. A second conductive charge storage area is formed in an area adjacent to the transfer gate electrode in the first conductive semiconductor area. A sidewall is formed on a side surface of the transfer gate electrode. An insulating film is formed to extend from a circumference surface of the sidewall on a side of the charge storage area to a position partially covering the upper part of the charge storage area. A first conductive charge storage layer is formed in the charge storage area by implanting first conductive impurities from above, into the charge storage area which is partially covered with the insulating film.
    Type: Application
    Filed: May 17, 2013
    Publication date: August 7, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Atsushi OHTA, Hitohisa Ono
  • Publication number: 20120241867
    Abstract: In a non-volatile semiconductor memory device, first element isolation insulation layers in a memory cell area are formed by burying a first oxide film in first element isolation trenches of the memory cell area. The top surface of the first oxide film is positioned at a level between the top surface of a semiconductor substrate and the top surface of a first gate electrode. Each of second element isolation insulation layers in a peripheral area includes a first oxide film embedded in the entirety of second element isolation trenches of the peripheral area, and a second oxide film formed on the first oxide film. The top surface of the first oxide film is at a higher level than the top surface of the semiconductor substrate. The top surface of the second oxide film is at a higher level than the top surface of a first conductor film.
    Type: Application
    Filed: March 15, 2012
    Publication date: September 27, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hitohisa ONO, Kazunori Nishikawa
  • Patent number: 8058734
    Abstract: A semiconductor device including a semiconductor substrate; a first insulating film formed on the semiconductor substrate including a contact hole opened therethrough; a lower plug filled in the contact hole having a recess defined in an upper portion thereof; a second insulating film including a via hole opened therethrough; a third insulating film formed on an inner surface of the via hole and extending in a predetermined depth from an upper edge of the via hole so as to reduce a cross sectional area thereof; and an upper plug filled in the via hole that has a protrusion formed on a lower portion thereof that conforms to the recess to electrically connect the upper and the lower plug.
    Type: Grant
    Filed: December 19, 2008
    Date of Patent: November 15, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hitohisa Ono
  • Publication number: 20090179332
    Abstract: A semiconductor device including a semiconductor substrate; a first insulating film formed on the semiconductor substrate including a contact hole opened therethrough; a lower plug filled in the contact hole having a recess defined in an upper portion thereof; a second insulating film including a via hole opened therethrough; a third insulating film formed on an inner surface of the via hole and extending in a predetermined depth from an upper edge of the via hole so as to reduce a cross sectional area thereof; and an upper plug filled in the via hole that has a protrusion formed on a lower portion thereof that conforms to the recess to electrically connect the upper and the lower plug.
    Type: Application
    Filed: December 19, 2008
    Publication date: July 16, 2009
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Hitohisa ONO