Abstract: In a manufacturing step in which a structure of target of screening is formed on a semiconductor substrate in the middle of manufacturing process before a semiconductor device is finished, screening of potential defects of a gate insulating film is performed for each wafer at one time so that the semiconductor device is caused to appear as an initial defective product when the finished semiconductor device is subjected to an electrical characteristic test. Provided are a semiconductor device, and a method of manufacturing a semiconductor device which enables reliable screening of potential defects in a short period of time.

Abstract: In a manufacturing step in which a structure of target of screening is formed on a semiconductor substrate in the middle of manufacturing process before a semiconductor device is finished, screening of potential defects of a gate insulating film is performed for each wafer at one time so that the semiconductor device is caused to appear as an initial defective product when the finished semiconductor device is subjected to an electrical characteristic test. Provided are a semiconductor device, and a method of manufacturing a semiconductor device which enables reliable screening of potential defects in a short period of time.

Abstract: In a manufacturing step in which a structure of target of screening is formed on a semiconductor substrate in the middle of manufacturing process before a semiconductor device is finished, screening of potential defects of a gate insulating film is performed for each wafer at one time so that the semiconductor device is caused to appear as an initial defective product when the finished semiconductor device is subjected to an electrical characteristic test. Provided are a semiconductor device, and a method of manufacturing a semiconductor device which enables reliable screening of potential defects in a short period of time.

Abstract: In order to inhibit forming cracks under a pad opening during ball bonding without increasing a chip size, a protective film includes a pad opening that exposes a part of a topmost layer metal film of the chip. A second metal film provided under the pad opening has a ring shape that defines a rectangular opening under the pad opening. The opening edge of the opening in the second metal film extends inwardly beyond the edge of the overlying pad opening. Vias connect the second metal film and the topmost layer metal film, and all of these vias are located outside the pad opening in plan view.

Abstract: In order to inhibit forming cracks under a pad opening during ball bonding without increasing a chip size, a protective film includes a pad opening that exposes a part of a topmost layer metal film. A second metal film provided under the pad opening has a ring shape that defines a rectangular opening under the pad opening. The opening edge of the opening in the second metal film extends inwardly beyond the edge of the overlying pad opening.

Abstract: In a manufacturing step in which a structure of target of screening is formed on a semiconductor substrate in the middle of manufacturing process before a semiconductor device is finished, screening of potential defects of a gate insulating film is performed for each wafer at one time so that the semiconductor device is caused to appear as an initial defective product when the finished semiconductor device is subjected to an electrical characteristic test. Provided are a semiconductor device, and a method of manufacturing a semiconductor device which enables reliable screening of potential defects in a short period of time.

Abstract: In a method of manufacturing a semiconductor device, a first photoresist layer is applied on a polycrystalline silicon layer formed on a semiconductor substrate. The first photoresist layer is then patterned and cured with UV rays. The polycrystalline silicon layer is etched, using the first photoresist layer as a mask, to form a gate electrode and a resistive film of the polycrystalline silicon layer. A second photoresist layer is applied on the cured first photoresist layer and patterned to form an opening portion exposing the first photoresist layer. Impurities are ion implanted through the opening portion in the polycrystalline silicon layer. The channeling of impurities implanted during the ion implantation is suppressed by the cured first photoresist layer.

Abstract: Provided is a method of manufacturing a semiconductor device, for suppressing channeling that may occur during ion implantation to a polycrystalline silicon layer (4), the method including: exposing, in an opening portion formed in a second photoresist layer (8), a first photoresist layer (5) that has been used for patterning the polycrystalline silicon layer (4); and implanting impurities by ion implantation with the first photoresist layer (5) being a mask for a gate electrode (4-1) formed of the polycrystalline silicon layer (4).

Abstract: A semiconductor device includes a P-type semiconductor substrate including a pad, a ground pad, and a power supply pad, a first N-type diffusion region formed on the P-type semiconductor substrate and connected to the pad, an internal circuit region formed on the P-type semiconductor substrate, and a minority carrier capture region formed between the first N-type diffusion region and the internal circuit region for capturing minority carriers in the P-type semiconductor substrate caused by a surge to the pad. The minority carrier capture region has a triple guard ring including a first P-type diffusion region, a second P-type diffusion region, and a second N-type diffusion region located between the first P-type diffusion region and the second P-type diffusion region. Each of the first P-type diffusion region and the second P-type diffusion region is connected to the ground pad respectively through metal film wirings that are separately formed.

Abstract: In order to inhibit a crack under a pad opening without increasing a chip size, a protective film (6) includes a pad opening (9) that exposes a part of a topmost layer metal film (3). The pad opening (9) is rectangular and square, and has an opening width of d0. A second metal film (2) has an opening under the pad opening (9). The opening is rectangular and square, and has an opening width of d4. A distance between an opening edge of the protective film (6) and an opening edge of the second metal film (2) is d3. The second metal film (2) has a rectangular donut shape, and protrudes to an inner side of the pad opening (9) by the distance d3.

Abstract: Provided is a semiconductor device capable of suppressing latch-up generation and formed within a small area. In a minority carrier capture region, a P-type diffusion region (22), an N-type well (24), and a P-type diffusion region (25) are formed on a surface of a P-type semiconductor substrate (27). An N-type diffusion region (23) is formed on a surface of the N-type well (24). And the N-type well (24) is located between the P-type diffusion region (22) and the P-type diffusion region (25). The P-type diffusion region (22) and the P-type diffusion region (25) are each connected to a ground pad (12) not by the shortest distance but respectively through metal film wirings arranged in a diverted way.

Abstract: A semiconductor device has semiconductor elements formed on a silicon substrate. A first one of the semiconductor elements has a region formed with a surface orientation of <100>. A second one of the semiconductor elements has a region formed with a surface orientation of <110>or <111>. A third one of the semiconductor elements has a region formed with a surface orientation different from the respective surface orientations of the regions of the first and second semiconductor elements.

Abstract: In order to effectively miniaturize elements of a semiconductor device while improving the characteristics of each semiconductor element on a single chip of a silicon substrate or without impairing the characteristics, at least three different silicon surface directions are applied to the elements. Accordingly, at least the characteristics required for each element, on which the surface directions have influence, can be determined as the best characteristics.

Abstract: A semiconductor device comprises a semiconductor substrate having a high voltage region and a low voltage region, at least a pair of adjacent high voltage MOS transistors disposed on the high voltage region of the semiconductor substrate, and low voltage MOS transistors disposed on the low voltage region of the semiconductor substrate. A first element isolator comprises a first shallow trench disposed on a surface of the low voltage, region of the semiconductor substrate, and a first dielectric embedded in the first shallow trench. A pair of second element isolators comprises two second shallow trenches spaced apart at an interval between a source region or a drain region of the pair of the adjacent high voltage MOS transistors and a source or a drain region of the other of the pair of the adjacent high voltage MOS transistors, and a second dielectric embedded in each of the second shallow trenches.

Abstract: In a semiconductor device in which high voltage MOS transistors and low voltage MOS transistors are mixedly mounted, a process is simplified and miniaturization thereof is achieved, without causing a parasitic transistor operation. An active region doped with a low impurity concentration of an impurity is formed in a channel region of a parasitic MOS transistor between two STI (shallow trench isolation) regions, and current flow between a source and a drain of the parasitic MOS transistor is cut off in a semiconductor device in which a high voltage MOS transistor and a microscopic low voltage MOS transistor are mixedly mounted on the same semiconductor substrate.

Abstract: To provide a manufacturing method for a semiconductor device, with which it is possible to prevent silicon oxynitride formed upon nitriding a first gate oxide film from inhibiting oxidation of a second gate oxide film to keep a high reliability of the second gate oxide film. When a first gate insulating film is removed for forming the second gate oxide film or when a silicon substrate is washed just before the formation of the second gate oxide film, treatment with an ammonia-hydrogen peroxide solution is added, whereby a silicon oxynitride film at a site where the second gate oxide film is formed can be removed prior to the formation of the second gate oxide film.