Patents by Inventor Hitoshi Arakaki

Hitoshi Arakaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7260511
    Abstract: A design aid apparatus includes an input section, an antenna propensity determination section, an output section, and a memory storing design data for a plurality of structures comprising an electronic device to be designed. Conductivity of a structure is determined based on conductivity information of the structure read out from the memory. The antenna propensity determination section determines a contact relation, which expresses a state of electrical contact between a conductive structure having conductivity and another conductive structure, based on information relating to shapes and arrangements of structures stored in the memory. A length of a route between a reference conductive structure and the conductive structure is determined. The antenna propensity of the electronic device is evaluated based on the route length.
    Type: Grant
    Filed: February 5, 2003
    Date of Patent: August 21, 2007
    Assignee: Fuji Xerox Co., Ltd.
    Inventors: Osamu Ueno, Hitoshi Arakaki
  • Patent number: 7068518
    Abstract: A circuit board device suppress with a small number of terminal elements unwanted irradiation originating between a power supply layer and a ground layer, even when a configuration of the power supply layer and the ground layer on the circuit board is complex, and a design support device thereof. The circuit board device has a power supply layer and a ground layer disposed in opposition to one another. A dielectric is disposed between the power supply layer and the ground layer. A power supply surface is divided into two power supply surfaces and by a slit having a generally T-shaped configuration to form power supply surface edges. The power supply surface edges retain across a predetermined length L a characteristic impedance present between the power supply layer and the ground layer. A terminal load is connected to a terminal portion of the power supply surface edges.
    Type: Grant
    Filed: March 14, 2001
    Date of Patent: June 27, 2006
    Assignee: Fuji Xerox Co., Ltd.
    Inventors: Osamu Ueno, Hitoshi Arakaki
  • Publication number: 20030212537
    Abstract: A design aid apparatus includes an input section, an antenna propensity determination section, an output section, and a memory storing design data for a plurality of structures comprising an electronic device to be designed. Conductivity of a structure is determined based on conductivity information of the structure read out from the memory. The antenna propensity determination section determines a contact relation, which expresses a state of electrical contact between a conductive structure having conductivity and another conductive structure, based on information relating to shapes and arrangements of structures stored in the memory. A length of a route between a reference conductive structure and the conductive structure is determined. The antenna propensity of the electronic device is evaluated based on the route length.
    Type: Application
    Filed: February 5, 2003
    Publication date: November 13, 2003
    Applicant: Fuji Xerox Co., Ltd.
    Inventors: Osamu Ueno, Hitoshi Arakaki
  • Publication number: 20010035799
    Abstract: A circuit board device suppress with a small number of terminal elements unwanted irradiation originating between a power supply layer and a ground layer, even when a configuration of the power supply layer and the ground layer on the circuit board is complex, and a design support device thereof. The circuit board device has a power supply layer and a ground layer disposed in opposition to one another. A dielectric is disposed between the power supply layer and the ground layer. A power supply surface is divided into two power supply surfaces and by a slit having a generally T-shaped configuration to form power supply surface edges. The power supply surface edges retain across a predetermined length L a characteristic impedance present between the power supply layer and the ground layer. A terminal load is connected to a terminal portion of the power supply surface edges.
    Type: Application
    Filed: March 14, 2001
    Publication date: November 1, 2001
    Inventors: Osamu Ueno, Hitoshi Arakaki