Abstract: A ferroelectric random access memory which comprises a memory cell matrix constituted by a plurality of 1T1C type memory cells of j rows and k columns, and having j bit lines, k word lines, and k plate lines, each of the plurality of memory cells being connected to one of the j bit lines and one pair of the k word lines and the k plate lines, a plate line drive circuit which selectively applies one of a first potential and a second potential having a higher potential level than the first potential to one plate line of the k plate lines, and an equalizing circuit which performs an equalizing process in which the first potential is applied to each of the j bit lines. The plate line drive circuit applies a third potential having a potential level between the first and second potentials to the one plate line, before starting the equalizing process by the equalizing circuit.