Abstract: Methods, apparatuses and systems to provide for technology to that includes a first power electronics module including a plurality of first transistors that are diagonally offset from each other, and a second power electronics module stacked on the first power electronics module. The second power electronics module includes second transistors that are diagonally offset from each other. The second transistors are staggered relative to the first transistors.

Abstract: A cooling assembly includes a housing defining a fluid chamber, wick structures arranged on an interior surface of the fluid chamber such that one or more flow channels are present therebetween, and a divider. The divider includes an outer frame comprising a first side and a second side and one or more bridging supports extending between and connecting the first side and the second side of the outer frame. The one or more bridging supports are aligned with the one or more flow channels between the wick structures. Each one of the one or more bridging supports define a plurality of vapor flow paths extending therethrough. The one or more bridging supports further define a plurality of vapor spaces between the one or more bridging supports that are aligned with the wick structures. The plurality of vapor flow paths are fluidly coupled to the vapor spaces.

Abstract: A system includes a power device unit coupled to a substrate. An upper cooling assembly is thermally coupled to an upper side of the substrate. A lower cooling assembly is thermally coupled to a lower side of the substrate. A gate driver unit is coupled to the upper cooling assembly. At least one upper via is formed through the upper cooling electrically coupling the gate driver unit to the power device unit. A capacitor unit is coupled to the lower cooling assembly. At least one lower via formed through the lower cooling assembly electrically coupling the capacitor unit to the power device unit.

Abstract: A manufacturing method of a semiconductor device includes preparing a silicon carbide substrate, growing an epitaxial layer, and forming a structure. The silicon carbide substrate has an upper surface on which an alignment mark having a recessed shape is disposed, and a perpendicular line to the upper surface is inclined with respect to a [0001] direction toward a [11-20] direction. The epitaxial layer is grown on the upper surface and covers the alignment mark. The structure is formed on or above the upper surface at a position apart from the alignment mark by an interval P in the [11-20] direction along the upper surface. The interval P satisfies a relationship of D/tan ? < P < 10D/tan ?, where D is a depth of the alignment mark and ? is an inclination angle of the perpendicular line with respect to the [0001] direction.

Abstract: Methods, apparatuses and systems provide for technology that includes a transistor assembly for a power electronics apparatus having a plurality of transistor pairs arranged in a common plane, where for each pair of transistors one transistor is flipped relative to the other transistor. The technology further includes a first lead frame arranged parallel to and electrically coupled to the first transistor in each transistor pair, a second lead frame coplanar to the first lead frame and arranged parallel to and electrically coupled to the second transistor in each transistor pair, and a plurality of output lead frames arranged coplanar to each other, where each respective output lead frame is arranged parallel to and electrically coupled to a respective one pair of the plurality of transistor pairs.

Abstract: Methods, apparatuses and systems to provide for technology to that includes a plurality of transistors including first transistors and second transistors. The first transistors are disposed opposite the second transistors in a lateral direction with a first space between the first transistors and the second transistors in the lateral direction. A gate driver is electrically connected to the plurality of transistors to operate the plurality of transistors. The gate driver has a first portion disposed between the first transistors and the second transistors in the first space.

Abstract: An integrated power electronic assembly includes a power electronic device, a cooling assembly offset from and thermally coupled to a second edge of the power electronic device, and a thermal spreader offset from and thermally coupled to a first edge of the power electronic device. The first edge of the power electronic device is opposite the second edge of the power electronic device, and the thermal spreader is thermally coupled to the cooling assembly.

Abstract: A cold plate includes a first cooling surface comprising a first cooling structure bonded to an inner surface of the first cooling surface, a second cooling surface comprising a second cooling structure bonded to an inner surface of the second cooling surface, a manifold comprising an internal cavity defined by a first length, a first width, and a first height, and a flow divider defined by a second length, a second width, and a second height. The manifold is enclosed by the first cooling surface and the second cooling surface on opposing surfaces of the manifold separated by the first height. The flow divider is positioned within the internal cavity of the manifold. The flow divider supports and separates the first cooling structure and the second cooling structure by a portion of the second height of the flow divider.

Abstract: A system includes a power device unit coupled to a substrate. An upper cooling assembly is thermally coupled to an upper side of the substrate. A lower cooling assembly is thermally coupled to a lower side of the substrate. A gate driver unit is coupled to the upper cooling assembly. At least one upper via is formed through the upper cooling electrically coupling the gate driver unit to the power device unit. A capacitor unit is coupled to the lower cooling assembly. At least one lower via formed through the lower cooling assembly electrically coupling the capacitor unit to the power device unit.

Abstract: A two-phase cold plate includes an outer enclosure having a fluid inlet and a fluid outlet each fluidly coupled to a fluid pathway, an inner enclosure having a vapor cavity and a vapor outlet, and one or more wicking structures disposed in the outer enclosure. The one or more wicking structures fluidly couple the fluid pathway of the outer enclosure with the vapor cavity of the inner enclosure and the one or more wicking structures comprise a plurality of nucleation sites configured to induce vaporization of a cooling fluid and facilitate vapor flow into the vapor cavity of the inner enclosure.

Abstract: An integrated power electronic assembly includes a power electronic device, a cooling assembly offset from and thermally coupled to a second edge of the power electronic device, and a thermal spreader offset from and thermally coupled to a first edge of the power electronic device. The first edge of the power electronic device is opposite the second edge of the power electronic device, and the thermal spreader is thermally coupled to the cooling assembly.

Abstract: A two-phase cold plate includes an outer enclosure having a fluid inlet and a fluid outlet each fluidly coupled to a fluid pathway, an inner enclosure having a vapor cavity and a vapor outlet, and one or more wicking structures disposed in the outer enclosure. The one or more wicking structures fluidly couple the fluid pathway of the outer enclosure with the vapor cavity of the inner enclosure and the one or more wicking structures comprise a plurality of nucleation sites configured to induce vaporization of a cooling fluid and facilitate vapor flow into the vapor cavity of the inner enclosure.

Abstract: Methods, apparatuses and systems provide technology that includes a first transistor, a second transistor stacked on the first transistor, at least one electrical conductor that is positioned between the first and second transistors and electrically connected to the first and second transistors, and a busbar that is electrically connected to the first and second transistors through the at least one electrical conductor.

Abstract: Methods, apparatuses and systems to provide for technology to that includes a plurality of transistors including first transistors and second transistors. The first transistors are disposed opposite the second transistors in a lateral direction with a first space between the first transistors and the second transistors in the lateral direction. A gate driver is electrically connected to the plurality of transistors to operate the plurality of transistors. The gate driver has a first portion disposed between the first transistors and the second transistors in the first space.

Abstract: A cold plate includes a first cooling surface comprising a first cooling structure bonded to an inner surface of the first cooling surface, a second cooling surface comprising a second cooling structure bonded to an inner surface of the second cooling surface, a manifold comprising an internal cavity defined by a first length, a first width, and a first height, and a flow divider defined by a second length, a second width, and a second height. The manifold is enclosed by the first cooling surface and the second cooling surface on opposing surfaces of the manifold separated by the first height. The flow divider is positioned within the internal cavity of the manifold. The flow divider supports and separates the first cooling structure and the second cooling structure by a portion of the second height of the flow divider.

Abstract: Methods, apparatuses and systems to provide for technology to that includes a first power electronics module including a plurality of first transistors that are diagonally offset from each other, and a second power electronics module stacked on the first power electronics module. The second power electronics module includes second transistors that are diagonally offset from each other. The second transistors are staggered relative to the first transistors.

Abstract: Methods, apparatuses and systems provide for technology that includes a transistor assembly for a power electronics apparatus having a plurality of transistor pairs arranged in a common plane, where for each pair of transistors one transistor is flipped relative to the other transistor. The technology further includes a first lead frame arranged parallel to and electrically coupled to the first transistor in each transistor pair, a second lead frame coplanar to the first lead frame and arranged parallel to and electrically coupled to the second transistor in each transistor pair, and a plurality of output lead frames arranged coplanar to each other, where each respective output lead frame is arranged parallel to and electrically coupled to a respective one pair of the plurality of transistor pairs.

Abstract: A cooling assembly includes a housing defining a fluid chamber, wick structures arranged on an interior surface of the fluid chamber such that one or more flow channels are present therebetween, and a divider. The divider includes an outer frame comprising a first side and a second side and one or more bridging supports extending between and connecting the first side and the second side of the outer frame. The one or more bridging supports are aligned with the one or more flow channels between the wick structures. Each one of the one or more bridging supports define a plurality of vapor flow paths extending therethrough. The one or more bridging supports further define a plurality of vapor spaces between the one or more bridging supports that are aligned with the wick structures. The plurality of vapor flow paths are fluidly coupled to the vapor spaces.