Patents by Inventor Hitoshi Hokari

Hitoshi Hokari has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7981734
    Abstract: A manufacturing method of a thin film transistor includes forming a pair of source/drain electrodes on a substrate, such that the source/drain electrodes define a gap therebetween; forming low resistance conductive thin films, which define a gap therebetween, on the source/drain electrodes; and forming an oxide semiconductor thin film layer on upper surface of the low resistance conductive thin films and in the gap defined between the low resistance conductive thin films so that the oxide semiconductor thin film layer functions as a channel. The low resistance conductive thin films and the oxide semiconductor thin film layer are etched so that side surfaces of the resistance conductive thin films and corresponding side surfaces of the oxide semiconductor thin film layer coincide with each other in a channel width direction of the channel. A gate electrode is mounted over the oxide semiconductor thin film layer.
    Type: Grant
    Filed: July 8, 2009
    Date of Patent: July 19, 2011
    Assignees: Kochi Industrial Promotion Center, Casio Computer Co., Ltd.
    Inventors: Mamoru Furuta, Takashi Hirao, Hiroshi Furuta, Tokiyoshi Matsuda, Takahiro Hiramatsu, Hiromitsu Ishii, Hitoshi Hokari, Motohiko Yoshida
  • Publication number: 20090269881
    Abstract: A manufacturing method of a thin film transistor includes forming a pair of source/drain electrodes on a substrate, such that the source/drain electrodes define a gap therebetween; forming low resistance conductive thin films, which define a gap therebetween, on the source/drain electrodes; and forming an oxide semiconductor thin film layer on upper surface of the low resistance conductive thin films and in the gap defined between the low resistance conductive thin films so that the oxide semiconductor thin film layer functions as a channel. The low resistance conductive thin films and the oxide semiconductor thin film layer are etched so that side surfaces of the resistance conductive thin films and corresponding side surfaces of the oxide semiconductor thin film layer coincide with each other in a channel width direction of the channel. A gate electrode is mounted over the oxide semiconductor thin film layer.
    Type: Application
    Filed: July 8, 2009
    Publication date: October 29, 2009
    Applicants: Kochi Industrial Promotion Center, Casio Computer Co., Ltd.
    Inventors: Mamoru FURUTA, Takashi Hirao, Hiroshi Furuta, Tokiyoshi Matsuda, Takahiro Hiramatsu, Hiromitsu Ishii, Hitoshi Hokari, Motohiko Yoshida
  • Publication number: 20090242887
    Abstract: A display substrate is disclosed comprising: a supporting substrate; an organic resin layer formed on the supporting substrate; and a transparent electrode formed on the organic resin layer, wherein the transparent electrode includes: a first layer containing a zinc oxide and formed in close contact with the organic resin layer; and a second layer containing a zinc oxide and which has a thickness thicker than a thickness of the first layer and is formed on the first layer, wherein the first layer is deposited by either one of a DC sputtering and a DC magnetron sputtering, and the second layer is deposited by any one of a radio frequency sputtering, a radio frequency magnetron sputtering, a radio frequency superimposing a DC sputtering, and a radio frequency superimposing a DC magnetron sputtering, and the display substrate is available, for example, as the substrate having a transparent electrode for counter electrode of liquid crystal display device.
    Type: Application
    Filed: March 27, 2009
    Publication date: October 1, 2009
    Applicants: CASIO COMPUTER CO., LTD., Kochi University of Technology
    Inventors: Tetsuya YAMAMOTO, Naoki YAMAMOTO, Hisao MAKINO, Akira UJIHARA, Yoshinori HIRASHIMA, Hiroaki IWAOKA, Hisashi AOKI, Hitoshi HOKARI, Motohiko YOSHIDA
  • Patent number: 7576394
    Abstract: A thin film transistor includes a substrate, and a pair of source/drain electrodes (i.e., a source electrode and a drain electrode) formed on the substrate and defining a gap therebetween. A pair of low resistance conductive thin films are provided such that each coats at least a part of one of the source/drain electrodes. The low resistance conductive thin films define a gap therebetween. An oxide semiconductor thin film layer is continuously formed on upper surfaces of the pair of low resistance conductive thin films and extends along the gap defined between the low resistance conductive thin films so as to function as a channel. Side surfaces of the oxide semiconductor thin film layer and corresponding side surfaces of the low resistance conductive thin films coincide with each other in a channel width direction of the channel.
    Type: Grant
    Filed: February 1, 2007
    Date of Patent: August 18, 2009
    Assignees: Kochi Industrial Promotion Center, Casio Computer Co., Ltd.
    Inventors: Mamoru Furuta, Takashi Hirao, Hiroshi Furuta, Tokiyoshi Matsuda, Takahiro Hiramatsu, Hiromitsu Ishii, Hitoshi Hokari, Motohiko Yoshida
  • Patent number: 7385224
    Abstract: A thin film transistor of the present invention includes a semiconductor thin film (8); a gate insulating film (7) formed on one surface of the semiconductor thin film (8); a gate electrode (6) formed to be opposite to the semiconductor thin film (8) through the gate insulating film (7); a source electrode (15) and a drain electrode (16) electrically connected to the semiconductor thin film (8); a source region; a drain region; and a channel region. The thin film transistor further includes an insulating film (9) formed on a peripheral portion corresponding to at least the source region and the drain region of the semiconductor thin film (8), and having a contact hole (10, 11) through which at least a part of each of the source region and the drain region is exposed wherein the source electrode (15) and the drain electrode (16) are connected to the semiconductor thin film (8) through the contact hole (10, 11).
    Type: Grant
    Filed: September 1, 2005
    Date of Patent: June 10, 2008
    Assignee: Casio Computer Co., Ltd.
    Inventors: Hiromitsu Ishii, Hitoshi Hokari, Motohiko Yoshida, Ikuhiro Yamaguchi
  • Publication number: 20070187760
    Abstract: A thin film transistor includes a substrate, and a pair of source/drain electrodes (i.e., a source electrode and a drain electrode) formed on the substrate and defining a gap therebetween. A pair of low resistance conductive thin films are provided such that each coats at least a part of one of the source/drain electrodes. The low resistance conductive thin films define a gap therebetween. An oxide semiconductor thin film layer is continuously formed on upper surfaces of the pair of low resistance conductive thin films and extends along the gap defined between the low resistance conductive thin films so as to function as a channel. Side surfaces of the oxide semiconductor thin film layer and corresponding side surfaces of the low resistance conductive thin films coincide with each other in a channel width direction of the channel.
    Type: Application
    Filed: February 1, 2007
    Publication date: August 16, 2007
    Applicants: Kochi Industrial Promotion Center, Casio Computer Co., Ltd.
    Inventors: Mamoru Furuta, Takashi Hirao, Hiroshi Furuta, Tokiyoshi Matsuda, Takahiro Hiramatsu, Hiromitsu Ishii, Hitoshi Hokari, Motohiko Yoshida
  • Publication number: 20060043447
    Abstract: A thin film transistor of the present invention includes a semiconductor thin film (8); a gate insulating film (7) formed on one surface of the semiconductor thin film (8); a gate electrode (6) formed to be opposite to the semiconductor thin film (8) through the gate insulating film (7); a source electrode (15) and a drain electrode (16) electrically connected to the semiconductor thin film (8); a source region; a drain region; and a channel region. The thin film transistor further includes an insulating film (9) formed on a peripheral portion corresponding to at least the source region and the drain region of the semiconductor thin film (8), and having a contact hole (10, 11) through which at least a part of each of the source region and the drain region is exposed wherein the source electrode (15) and the drain electrode (16) are connected to the semiconductor thin film (8) through the contact hole (10, 11).
    Type: Application
    Filed: September 1, 2005
    Publication date: March 2, 2006
    Applicant: CASIO COMPUTER CO., LTD.
    Inventors: Hiromitsu Ishii, Hitoshi Hokari, Motohiko Yoshida, Ikuhiro Yamaguchi