Abstract: A semiconductor package of an embodiment includes: a wiring substrate having a first surface and a second surface on a side opposite to the first surface; at least one semiconductor chip provided in plurality at different heights from the first surface in a vertical direction; a sealing resin covering the first surface of the wiring substrate and surfaces of the at least one semiconductor chip; a layer formed over a top layer of the at least one semiconductor chip; and an external terminal provided on the second surface of the wiring substrate. The wiring substrate is electrically connectable with a printed wiring board through the external terminal.

Abstract: A semiconductor package of an embodiment includes a wiring substrate, a semiconductor chip provided on an upper surface of the wiring substrate, a sealing resin covering surfaces of the wiring substrate and the semiconductor chip, an infrared reflection layer containing any of aluminum, aluminum oxide, and titanium oxide, and an external terminal provided on a lower surface of the wiring substrate. The wiring substrate is electrically connectable with a printed wiring board through the external terminal. The infrared reflection layer is provided to the sealing resin on an upper side of a surface of the semiconductor chip on a side opposite to an upper surface of the wiring substrate.

Abstract: A semiconductor device includes a semiconductor chip including a wiring layer formed on a first side, a first pad formed so as to protrude from a surface of a passivation film on the first side, and an interlayer film formed between the first side and the wiring layer on one side and the passivation film and the first pad on another side, and a mounting substrate including a second pad on the second side, and the first pad and the second pad are in contact with each other. A thickness of the interlayer film between the wiring layer and the first pad is 0.5 to 2.8 ?m. The first pad is disposed between formation regions of internal circuits provided on the semiconductor chip.

Abstract: A semiconductor package of an embodiment includes a wiring substrate, a semiconductor chip provided on an upper surface of the wiring substrate, a sealing resin covering surfaces of the wiring substrate and the semiconductor chip, an infrared reflection layer containing any of aluminum, aluminum oxide, and titanium oxide, and an external terminal provided on a lower surface of the wiring substrate. The wiring substrate is electrically connectable with a printed wiring board through the external terminal. The infrared reflection layer is provided to the sealing resin on an upper side of a surface of the semiconductor chip on a side opposite to an upper surface of the wiring substrate.

Abstract: A semiconductor package of an embodiment includes a wiring substrate, a semiconductor chip provided on an upper surface of the wiring substrate, a sealing resin covering surfaces of the wiring substrate and the semiconductor chip, an infrared reflection layer containing any of aluminum, aluminum oxide, and titanium oxide, and an external terminal provided on a lower surface of the wiring substrate. The wiring substrate is electrically connectable with a printed wiring board through the external terminal. The infrared reflection layer is provided to the sealing resin on an upper side of a surface of the semiconductor chip on a side opposite to an upper surface of the wiring substrate.

Abstract: A semiconductor package of an embodiment includes a wiring substrate, a semiconductor chip provided on an upper surface of the wiring substrate, a sealing resin covering surfaces of the wiring substrate and the semiconductor chip, an infrared reflection layer containing any of aluminum, aluminum oxide, and titanium oxide, and an external terminal provided on a lower surface of the wiring substrate. The wiring substrate is electrically connectable with a printed wiring board through the external terminal. The infrared reflection layer is provided to the sealing resin on an upper side of a surface of the semiconductor chip on a side opposite to an upper surface of the wiring substrate.

Abstract: A semiconductor device has a plurality of insulated gate field effect transistors on a semiconductor substrate. A SAC contact hole is formed between two gates of the insulated gate field effect transistors. A side portion of the SAC contact hole is separated from two gates of the insulated gate field effect transistors by a side wall dielectric film and a dielectric film. A polycrystalline silicon plug having a U-shaped section structure is formed in a bottom portion of the SAC contact hole. A barrier metal film is formed on the polycrystalline silicon plug. A metal plug is buried on the barrier metal film so that covering on the SAC contact hole.