Patents by Inventor Hitoshi Imagawa

Hitoshi Imagawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5594724
    Abstract: A transmission convergence sublayer multiplex generating apparatus includes a TC layer calculating section, a TC layer information storing section for storing TC layer information in correspondence with each path, and an ATM layer information storing section for storing ATM layer information in correspondence with each path.
    Type: Grant
    Filed: September 1, 1995
    Date of Patent: January 14, 1997
    Assignees: NEC Corporation, Nippon Telegraph and Telephone Corporation
    Inventors: Masao Akata, Takao Miura, Takeshi Ogawa, Yukihiro Doi, Isao Higashi, Hitoshi Imagawa
  • Patent number: 5022025
    Abstract: A self-routing switch in which a plurality of switching stages, each having a plurality of switching elements, are sequentially connected by substitute links, wherein additional two input terminals and additional two output terminals are provided in each switching element of at least the last plural switching stages of the switch, and the output terminals and input terminals of the same line position between these last plural switching stages are connected by equivalent links, respectively. When information data appended with a destination address and judge times, as routing information, is input into the switch, one of the bits in the destination address is selected as a judge bit on the basis of the judge times, and the output terminal to which the information data is to be output is selected according to the value of the judge bit.
    Type: Grant
    Filed: February 13, 1989
    Date of Patent: June 4, 1991
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Shigeo Urushidani, Hitoshi Imagawa
  • Patent number: 4864558
    Abstract: In a self-routing switch which comprises a plurality of switching stages inserted between pluralities of input and output lines and cascade-connected by pluralities of input and output links, each switching stage includes a plurality of cascade-connected store/switch elements. Each store/switch element of each switching stage outputs an information data input thereto from the corresponding input link to the corresponding output link or shifts the input information data through a predetermined number of cascade-connected elements and outputs it to the corresponding output link, in accordance with a portion of routing information contained in the input information data, which portion corresponds to the switching stage.
    Type: Grant
    Filed: November 17, 1987
    Date of Patent: September 5, 1989
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Hitoshi Imagawa, Shigeo Urushidani, Koichi Hagishima
  • Patent number: 4328398
    Abstract: A digital multi-frequency receiver for the use in an electronic telephone exchange system for detecting MF signals (700,900, 1100, 1300, 1500 and 1700 Hz) in the CCITT No. 5 system. The digital multi-frequency receiver comprises a recursive digital filter for detecting each of the MF signals on a time divisional basis, an absolute value circuit for providing the absolute value of the output of the recursive digital filter, a comparator for comparing the output of the absolute value circuit with a variable threshold to provide the detected MF signal information, and a circuit for providing the variable threshold by selecting the maximum value from among, (i) the predetermined fixed value, (ii) the product of the value .alpha. which is less than but close to 1 and the maximum value of the variable threshold circuit in a preceding frame, and (iii) the maximum value of the output of the absolute value circuit in a present frame.
    Type: Grant
    Filed: May 9, 1980
    Date of Patent: May 4, 1982
    Assignees: Oki Electric Industry Co., Ltd., Nippon Telegraph & Telephone Public Corp.
    Inventors: Masaharu Kawaguchi, Yoshikatu Shiraishi, Kazuhiro Maruyama, Hitoshi Imagawa, Yoshimasa Kaneko
  • Patent number: 4245325
    Abstract: Disclosed is a digital multifrequency signaling receiving system in which a first operation device executes an operation to multiply multifrequency signals composed of N samples as input signals by a window function including coefficients required for fast Fourier transform. An output produced at the first operation device, as a sample signal, is subjected to fast Fourier transformation at a second operation device which includes a subtractor and a logic circuit. In the subtractor, the sample signals are delayed N/2 samples to halve the number of sample signals. The logic circuit executes an operation for the sample signals, taking advantage of the fact that some frequencies of the outputs of the Fourier transform are represented as the conjugate complex of the other outputs of the Fourier transform.
    Type: Grant
    Filed: February 15, 1979
    Date of Patent: January 13, 1981
    Assignee: Nippon Telegraph and Telephone Public Corporation
    Inventors: Shiro Kikuchi, Hitoshi Imagawa, Yasumasa Iwase