Abstract: According to one embodiment, a semiconductor device includes: first, second, and third lead frames; a first transistor which is GaN transistor provided on the first lead frame and electrically connected to the first lead frame; a second transistor which is GaN transistor provided on the second lead frame and electrically connected to the third lead frame; a third transistor which is MOS transistor provided on the third lead frame and electrically connected to the third lead frame and the first transistor; a fourth transistor which is MOS transistor provided on the second lead frame and electrically connected to the second lead frame and the second transistor; and a capacitor electrically connected to the first and the second lead frame; wherein the first, the third, the second, and the fourth transistor are arranged side by side in this order in a first direction.

Abstract: In an arithmetic method according to an embodiment, executing an arithmetic operation includes performing first simulation when a control target is driven in a first drive pattern using a simulation model in which an element model is a model in which electrical characteristics of a switching element are resistance characteristics, extracting first time-series data of a drive signal output from a control model in the first simulation, and performing second simulation when the control target is driven in the first drive pattern using the simulation model in which the control model is a model from which the first time-series data is output along a time series and in which the element model is a model in which power loss including switching loss that occurs when a state of the switching element is switched can be output.

Abstract: According to one embodiment, a semiconductor device includes a first switch provided with a first electrode and a second electrode, a second switch provided with a third electrode and a fourth electrode, a first capacitor including a first wiring layer connected to the third electrode, a second wiring layer connected to the first electrode, and a first dielectric layer, a substrate, a third wiring layer connected to the first wiring layer and applied with a first voltage, a fourth wiring layer connected to the second wiring layer and applied with a second voltage, and a fifth wiring layer connected to the second and fourth electrodes, and applied with a third voltage. The first capacitor is arranged between the first and second switches. The third electrode faces the first electrode. The fourth electrode faces the second electrode and is connected to the second electrode in series.

Abstract: First and second switches are electrically connected. A capacitor includes first and second terminals and a capacitor having an end electrically connected to the first terminal and another end electrically connected to the second terminal. The first and second terminals are electrically connected to the first and second switches, respectively. The capacitor is located above the first and second switches along a first direction. A width of the capacitor in a second direction that is a direction connecting the end and the another end of the capacitor is larger than a width of a set of the first and second switches in the second direction. The first switch and the second switch are arranged in the second direction.

Abstract: According to one embodiment, a semiconductor device includes: first, second, and third lead frames; a first transistor which is GaN transistor provided on the first lead frame and electrically connected to the first lead frame; a second transistor which is GaN transistor provided on the second lead frame and electrically connected to the third lead frame; a third transistor which is MOS transistor provided on the third lead frame and electrically connected to the third lead frame and the first transistor; a fourth transistor which is MOS transistor provided on the second lead frame and electrically connected to the second lead frame and the second transistor; and a capacitor electrically connected to the first and the second lead frame; wherein the first, the third, the second, and the fourth transistor are arranged side by side in this order in a first direction.

Abstract: According to one embodiment, a semiconductor device includes: a first conductive layer provided on a substrate; a second conductive layer provided on the substrate and to which a first voltage is supplied; a third conductive layer corresponding to an output node and provided on the substrate between the first conductive layer and the second conductive layer; a first switching device provided above the first conductive layer and including a first terminal to which a second voltage higher than the first voltage is supplied and a second terminal connected to the third conductive layer; and a second switching device provided above the second conductive layer and including a third terminal connected to the third conductive layer and a fourth terminal connected to the second conductive layer.

Abstract: According to one embodiment, a semiconductor device has a first terminal, and a second terminal in which a first groove portion is formed through an upper face thereof. Also, the semiconductor device has a first transistor that has a first drain electrode electrically connected to the first terminal, a first source electrode, and a nitride semiconductor layer, and is provided in the first groove portion. Further still, the semiconductor device includes a second transistor that has a second drain electrode electrically connected to the second terminal and a second source electrode electrically connected to the first source electrode.

Abstract: An inspection device for performing operation inspection of a circuit including a transistor may include, but is not limited to, a standard calculating circuitry and a standard determining circuitry. The standard calculating circuitry is configured to calculate an electrical standard of the transistor on the basis of information on specifications of the transistor. The standard determining circuitry is configured to determine whether an inspection data group including temporal data of a value of current flowing in the transistor in a predetermined time range and of a value of voltage applied to the transistor satisfies the electrical standard and to output data which is determined not to satisfy the electrical standard in the inspection data group.

Abstract: According to one embodiment, a simulation apparatus is disclosed. The simulation apparatus includes a storage device storing data relating to a thermal equivalent circuit of a semiconductor device. The simulation apparatus further includes an estimation device estimating a time-dependent change in thermal characteristics of the semiconductor device by using the data. The thermal equivalent circuit includes a first thermal equivalent circuit corresponding to a lower-surface-side part of the semiconductor device. The thermal equivalent circuit further includes a second thermal equivalent circuit connected to the first thermal equivalent circuit and corresponding to an upper-surface-side part of the semiconductor device.

Abstract: A non-transitory computer readable recording medium includes simulation data input into a computing device executing a simulation of a semiconductor device, wherein the simulation data includes part shape information describing shape and terminal information of the semiconductor device, logical model information describing operation and connection information of an element in the semiconductor device, and functional block information describing positional information of a functional block in the semiconductor device, and the computing device causes the part shape information, the logical model information, and the functional block information to correspond to each other to execute the simulation of the semiconductor device.

Abstract: An arithmetic method by a computer according to the present embodiment includes model generating, execution processing, and electromagnetic interference noise generating. The model generating generates a model including a circuit model configured by a plurality of element models connected to each other and a motor model driven by the circuit model. The execution processing computes a motor current of the motor model generated in each of first calculating steps over time by using information on electrical characteristics of each element model. The electromagnetic interference noise generating generates electromagnetic interference noise in accordance with a frequency at a predetermined measurement point in the model in each of predetermined time segments in a measurement period, and generates an electromagnetic interference noise level at each frequency in the measurement period based on an electromagnetic interference noise level in accordance with the frequency in each of the time segments.

Abstract: A recording medium includes simulation data input into a computing device executing a simulation of a semiconductor device, wherein the simulation data includes part shape information describing a shape of a part included in a simulation target circuit, model information describing operation and connection information of the simulation target circuit, and symbol information of the part included in the simulation target circuit, and the computing device causes the part shape information, the model information, and the symbol information to correspond to each other to execute the simulation of the semiconductor device.

Abstract: According to one embodiment, a simulation apparatus is disclosed. The simulation apparatus includes a storage device storing data relating to a thermal equivalent circuit of a semiconductor device. The simulation apparatus further includes an estimation device estimating a time-dependent change in thermal characteristics of the semiconductor device by using the data. The thermal equivalent circuit includes a first thermal equivalent circuit corresponding to a lower-surface-side part of the semiconductor device. The thermal equivalent circuit further includes a second thermal equivalent circuit connected to the first thermal equivalent circuit and corresponding to an upper-surface-side part of the semiconductor device.

Abstract: A recording medium includes simulation data input into a computing device executing a simulation of a semiconductor device, wherein the simulation data includes part shape information describing a shape of a part included in a simulation target circuit, model information describing operation and connection information of the simulation target circuit, and symbol information of the part included in the simulation target circuit, and the computing device causes the part shape information, the model information, and the symbol information to correspond to each other to execute the simulation of the semiconductor device.

Abstract: A non-transitory computer readable recording medium includes simulation data input into a computing device executing a simulation of a semiconductor device, wherein the simulation data includes part shape information describing shape and terminal information of the semiconductor device, logical model information describing operation and connection information of an element in the semiconductor device, and functional block information describing positional information of a functional block in the semiconductor device, and the computing device causes the part shape information, the logical model information, and the functional block information to correspond to each other to execute the simulation of the semiconductor device.

Abstract: An arithmetic method according to the present embodiment comprises a model creation step, an execution processing step, and a thermal model creation step. The model creation step creates a circuit model in which a plurality of element models each having information on electrical characteristics of a switching element are connected to each other. The execution processing step computes, by using the information on the electrical characteristics of each of the element models, a power generated at each time step by switching of the element model with respect to a predetermined time-series input value in time series. The thermal model creation step creates a thermal model that outputs an output value based on an integrated value obtained by integrating the power generated at the each time step, in accordance with switching of the element model.

Abstract: A printed circuit board of an embodiment includes a board, a first ground plane provided on a first face of the board and having a first opening, a first wiring provided above the first ground plane, a second ground plane provided on a second face facing the first face of the board and having a second opening, a second wiring provided above the second ground plane, and a third wiring penetrating the board between the first opening and the second opening and connecting the first wiring and the second wiring. The third wiring is provided in the first opening and in the second opening when viewed from a direction perpendicular to the first face of the board.

Abstract: A printed circuit board of an embodiment includes a board, a first ground plane provided on a first face of the board and having a first opening, a first wiring provided above the first ground plane, a second ground plane provided on a second face facing the first face of the board and having a second opening, a second wiring provided above the second ground plane, and a third wiring penetrating the board between the first opening and the second opening and connecting the first wiring and the second wiring. The third wiring is provided in the first opening and in the second opening when viewed from a direction perpendicular to the first face of the board.