Abstract: A non-transitory computer readable recording medium includes simulation data input into a computing device executing a simulation of a semiconductor device, wherein the simulation data includes part shape information describing shape and terminal information of the semiconductor device, logical model information describing operation and connection information of an element in the semiconductor device, and functional block information describing positional information of a functional block in the semiconductor device, and the computing device causes the part shape information, the logical model information, and the functional block information to correspond to each other to execute the simulation of the semiconductor device.

Abstract: An arithmetic method by a computer according to the present embodiment includes model generating, execution processing, and electromagnetic interference noise generating. The model generating generates a model including a circuit model configured by a plurality of element models connected to each other and a motor model driven by the circuit model. The execution processing computes a motor current of the motor model generated in each of first calculating steps over time by using information on electrical characteristics of each element model. The electromagnetic interference noise generating generates electromagnetic interference noise in accordance with a frequency at a predetermined measurement point in the model in each of predetermined time segments in a measurement period, and generates an electromagnetic interference noise level at each frequency in the measurement period based on an electromagnetic interference noise level in accordance with the frequency in each of the time segments.

Abstract: A recording medium includes simulation data input into a computing device executing a simulation of a semiconductor device, wherein the simulation data includes part shape information describing a shape of a part included in a simulation target circuit, model information describing operation and connection information of the simulation target circuit, and symbol information of the part included in the simulation target circuit, and the computing device causes the part shape information, the model information, and the symbol information to correspond to each other to execute the simulation of the semiconductor device.

Abstract: According to one embodiment, a simulation apparatus is disclosed. The simulation apparatus includes a storage device storing data relating to a thermal equivalent circuit of a semiconductor device. The simulation apparatus further includes an estimation device estimating a time-dependent change in thermal characteristics of the semiconductor device by using the data. The thermal equivalent circuit includes a first thermal equivalent circuit corresponding to a lower-surface-side part of the semiconductor device. The thermal equivalent circuit further includes a second thermal equivalent circuit connected to the first thermal equivalent circuit and corresponding to an upper-surface-side part of the semiconductor device.

Abstract: A non-transitory computer readable recording medium includes simulation data input into a computing device executing a simulation of a semiconductor device, wherein the simulation data includes part shape information describing shape and terminal information of the semiconductor device, logical model information describing operation and connection information of an element in the semiconductor device, and functional block information describing positional information of a functional block in the semiconductor device, and the computing device causes the part shape information, the logical model information, and the functional block information to correspond to each other to execute the simulation of the semiconductor device.

Abstract: A recording medium includes simulation data input into a computing device executing a simulation of a semiconductor device, wherein the simulation data includes part shape information describing a shape of a part included in a simulation target circuit, model information describing operation and connection information of the simulation target circuit, and symbol information of the part included in the simulation target circuit, and the computing device causes the part shape information, the model information, and the symbol information to correspond to each other to execute the simulation of the semiconductor device.

Abstract: An arithmetic method according to the present embodiment comprises a model creation step, an execution processing step, and a thermal model creation step. The model creation step creates a circuit model in which a plurality of element models each having information on electrical characteristics of a switching element are connected to each other. The execution processing step computes, by using the information on the electrical characteristics of each of the element models, a power generated at each time step by switching of the element model with respect to a predetermined time-series input value in time series. The thermal model creation step creates a thermal model that outputs an output value based on an integrated value obtained by integrating the power generated at the each time step, in accordance with switching of the element model.

Abstract: A printed circuit board of an embodiment includes a board, a first ground plane provided on a first face of the board and having a first opening, a first wiring provided above the first ground plane, a second ground plane provided on a second face facing the first face of the board and having a second opening, a second wiring provided above the second ground plane, and a third wiring penetrating the board between the first opening and the second opening and connecting the first wiring and the second wiring. The third wiring is provided in the first opening and in the second opening when viewed from a direction perpendicular to the first face of the board.

Abstract: A printed circuit board of an embodiment includes a board, a first ground plane provided on a first face of the board and having a first opening, a first wiring provided above the first ground plane, a second ground plane provided on a second face facing the first face of the board and having a second opening, a second wiring provided above the second ground plane, and a third wiring penetrating the board between the first opening and the second opening and connecting the first wiring and the second wiring. The third wiring is provided in the first opening and in the second opening when viewed from a direction perpendicular to the first face of the board.