Abstract: A data processing apparatus reduces the number of steps performed by a processor so as to achieve a high-speed operation. A data memory, which stores data to be calculated by the processor, includes a first memory part and a second memory part each of which is connected to the same data bus and address bus. An address structure of the second memory part is identical to an address structure of the first memory part. One of first address data output from the processor and second address data provided from an external device is selectively provided to the first and the second memory parts so that the first address data is provided to the first memory part when the second address data is provided to the second memory part, and vice versa. A sort circuit rearranges the data output from the processor in a predetermined order so that the rearranged data is provided to the processor in the order of use by the processor.

Abstract: Perspective transformation is performed on X, Y, Z coordinate data Xe, Ye and Ze in a view volume in a viewpoint coordinate system so as to obtain X, Y, Z coordinate data Xs, Ys and Zs in a screen coordinate system. The view volume being defined by a front clipping plane and a rear clipping plane, in which: Zs=1-CZF/Ze, or Zs=CZF/Ze, or Zs=1/Ze when a difference between a Z value CZF at the front clipping plane and a Z value CZB at the rear clipping plane is substantially large. Data bits of the Zs are shifted depending on the Z value CZF, when the difference between the Z value CZF at the front clipping plane and the Z value CZB at the rear clipping plane is substantially large where the view volume is defined by the front clipping plane and the rear clipping plane, or when the view volume is defined only by the front clipping plane. Then, a hidden-surface removal operation is performed using a Z-buffer method in accordance with the Zs.