Abstract: An imaging device includes a pixel array part having a plurality of pixels that perform photoelectric conversion, a converter that converts an analog pixel signal output from the pixel array part into digital pixel data, a first signal processing unit that performs first signal processing on the digital pixel data, a second signal processing unit that performs second signal processing that is at least partly shared by the first signal processing on the digital pixel data or data that has been subjected to at least a part of the first signal processing, a recognition processing unit that performs predetermined recognition processing on the basis of output data of the second signal processing unit, and an output interface unit that outputs at least one of output data of the first signal processing unit and the output data of the recognition processing unit.

Abstract: Signal processing is performed using a built-in memory. An imaging apparatus includes: a pixel array unit that includes a plurality of pixels performing photoelectric conversion; a converter that converts an analog pixel signal output from the pixel array unit into digital image data; an image processing unit that performs image processing on the digital image data; and a storage unit that includes a plurality of regions for which a power distribution state is able to be selectively designated, and stores at least the digital image data output by the image processing unit.

Abstract: An imaging device includes a pixel array part having a plurality of pixels that perform photoelectric conversion, a converter that converts an analog pixel signal output from the pixel array part into digital pixel data, a first signal processing unit that performs first signal processing on the digital pixel data, a second signal processing unit that performs second signal processing that is at least partly shared by the first signal processing on the digital pixel data or data that has been subjected to at least a part of the first signal processing, a recognition processing unit that performs predetermined recognition processing on the basis of output data of the second signal processing unit, and an output interface unit that outputs at least one of output data of the first signal processing unit and the output data of the recognition processing unit.

Abstract: Certain aspects of an apparatus and method for interconnection may include an interconnection section, a request processing section and a response processing section. The interconnection section may be configured to transfer a request from a master interface bus to a slave interface bus and to transfer a response from the slave interface bus to the master interface bus. A slot number within the request specifies a time slot during which the interconnection section may be permitted to transfer the response to the master interface bus. The request commands the processing section to load the slot number into a management table. The response commands the response processing section to read out the slot number from the management table.

Abstract: An instruction fetch apparatus is disclosed which includes: a program counter configured to manage the address of an instruction targeted to be executed in a program in which instructions belonging to a plurality of instruction sequences are placed sequentially; a change designation register configured to designate a change of an increment value on the program counter; an increment value register configured to hold the changed increment value; and an addition control section configured such that if the change designation register designates the change of the increment value on the program counter, then the addition control section increments the program counter based on the changed increment value held in the increment value register, the addition control section further incrementing the program counter by an instruction word length if the change designation register does not designate any change of the increment value on the program counter.

Abstract: An interconnection apparatus includes: a buffer; a request processing section; a response processing section; and an interconnection section.

Abstract: An address translation circuit includes an area address holding section, an invert flag holding section, a match detection section, and a bit conversion section. The area address holding section holds at least part of a translation target address as an area address. The invert flag holding section holds an invert flag specifying whether or not part of said translation target address is to be inverted. The match detection section detects a match between a predetermined part of at least one bit in an input address on the one hand, and said area address held by said area address holding section on the other hand. If a match is detected by said match detection section and if said invert flag held by said invert flag holding section specifies that part of said translation target address is to be inverted, the bit inversion section inverts a predetermined bit part in said input address before outputting the bit-inverted address.

Abstract: An instruction fetch apparatus is disclosed which includes: a detection state setting section configured to set the execution state of a program of which an instruction prefetch timing is to be detected; a program execution state generation section configured to generate the current execution state of the program; an instruction prefetch timing detection section configured to detect the instruction prefetch timing in the case of a match between the current execution state of the program and the set execution state thereof upon comparison therebetween; and an instruction prefetch section configured to prefetch the next instruction upon detection of the instruction prefetch timing.

Abstract: An instruction fetch apparatus is disclosed which includes: a program counter configured to manage the address of an instruction targeted to be executed in a program in which instructions belonging to a plurality of instruction sequences are placed sequentially; a change designation register configured to designate a change of an increment value on the program counter; an increment value register configured to hold the changed increment value; and an addition control section configured such that if the change designation register designates the change of the increment value on the program counter, then the addition control section increments the program counter based on the changed increment value held in the increment value register, the addition control section further incrementing the program counter by an instruction word length if the change designation register does not designate any change of the increment value on the program counter.

Abstract: Disclosed herein is an address translation circuit including an area address holding section configured to hold at least part of a translation target address as an area address; a translation flag holding section configured to hold a translation flag specifying whether or not the translation target address is to be translated; a match detection section configured to detect a match between a predetermined part of at least one bit in an input address on the one hand, and the area address held by the area address holding section on the other hand; and a translation section configured such that if a match is detected by the match detection section and if the translation flag held by the translation flag holding section specifies that the translation target address is to be translated, then the translation section translates the input address into an address paired with the input address before outputting the paired address.