Patents by Inventor Hitoshi Kokubun

Hitoshi Kokubun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6955966
    Abstract: A method of manufacturing a mask ROM for storing quaternary data enables short turn around time, makes refining cell sizes simple, and enables stable reading of data. Gaps are formed between word lines in the memory cell transistors and two diffusion areas in accordance with quaternary write data. A current runs between these diffusion areas only when one of these two areas which is adjacent a gap is used as a drain. Accordingly, quaternary data can be read by a first reading when the first diffusion area is a source and the other diffusion area is a drain, and by reading a second reading when the first diffusion area is used as a drain and the other diffusion area as a source.
    Type: Grant
    Filed: July 21, 2004
    Date of Patent: October 18, 2005
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Noboru Egawa, Hitoshi Kokubun
  • Publication number: 20040259301
    Abstract: A method of manufacturing a mask ROM for storing quaternary data enables short turn around time, makes refining cell sizes simple, and enables stable reading of data. Gaps are formed between word lines in the memory cell transistors and two diffusion areas in accordance with quaternary write data. A current runs between these diffusion areas only when one of these two areas which is adjacent a gap is used as a drain. Accordingly, quaternary data can be read by a first reading when the first diffusion area is a source and the other diffusion area is a drain, and by reading a second reading when the first diffusion area is used as a drain and the other diffusion area as a source.
    Type: Application
    Filed: July 21, 2004
    Publication date: December 23, 2004
    Inventors: Noboru Egawa, Hitoshi Kokubun
  • Patent number: 6780710
    Abstract: A method of manufacturing a mask ROM for storing quaternary data enables short turn around time, makes refining cell sizes simple, and enables stable reading of data. Gaps are formed between word lines in the memory cell transistors and two diffusion areas. Impurities are doped into these gaps in accordance with quaternary write data when data is written. A current runs between these diffusion areas only when one of these two areas into which impurities have been doped is used as a drain. Accordingly, quaternary data can be read by a first reading when the first diffusion area is a source and the other diffusion area is a drain, and by reading a second reading when the first diffusion area is used as a drain and the other diffusion area as a source.
    Type: Grant
    Filed: August 29, 2002
    Date of Patent: August 24, 2004
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Noboru Egawa, Hitoshi Kokubun
  • Publication number: 20020197797
    Abstract: The mask ROM for storing quaternary data that enables a short turn around time, makes refining cell sizes simple, and that enables stable reading of data. Gaps are formed between word lines in the memory cell transistors and two n+ diffusion areas. n+ impurities are doped into these gaps in accordance with quaternary write data when data is written. A current runs between these diffusion areas only when one of these two areas into which impurities have been doped is used as a drain. Accordingly, quaternary data can be read by reading once when one diffusion area is a source and the other diffusion area is a drain and by reading again when the first diffusion area is used as a drain and the other as a source.
    Type: Application
    Filed: August 29, 2002
    Publication date: December 26, 2002
    Inventors: Noboru Egawa, Hitoshi Kokubun
  • Patent number: 6487119
    Abstract: The mask ROM for storing quaternary data that enables a short turn around time, makes refining cell sizes simple, and that enables stable reading of data. Gaps are formed between word lines in the memory cell transistors and two n+ diffusion areas. n+ impurities are doped into these gaps in accordance with quaternary write data when data is written. A current runs between these diffusion areas only when one of these two areas into which impurities have been doped is used as a drain. Accordingly, quaternary data can be read by reading once when one diffusion area is a source and the other diffusion area is a drain and by reading again when the first diffusion area is used as a drain and the other as a source.
    Type: Grant
    Filed: May 11, 2001
    Date of Patent: November 26, 2002
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Noboru Egawa, Hitoshi Kokubun
  • Publication number: 20020060927
    Abstract: The mask ROM for storing quaternary data that enables a short turn around time, makes refining cell sizes simple, and that enables stable reading of data. Gaps are formed between word lines in the memory cell transistors and two n+ diffusion areas. n+ impurities are doped into these gaps in accordance with quaternary write data when data is written. A current runs between these diffusion areas only when one of these two areas into which impurities have been doped is used as a drain. Accordingly, quaternary data can be read by reading once when one diffusion area is a source and the other diffusion area is a drain and by reading again when the first diffusion area is used as a drain and the other as a source.
    Type: Application
    Filed: May 11, 2001
    Publication date: May 23, 2002
    Inventors: Noboru Egawa, Hitoshi Kokubun
  • Patent number: 6233168
    Abstract: A non-volatile semiconductor memory decreases a parasitic current as much as possible without using an electric separation means. This nonvolatile semiconductor storage apparatus has multiple memory cells rows having multiple memory cell transistors M1, M2 . . . whose gates are connected to word lines WL1, WL2 . . . , respectively, and whose sources and drains are serially connected. This non-volatile semiconductor storage apparatus also has multiple column lines SBL0, SVL0, SVL1, SBL1 . . . which connect the connection nodes between the sources and drains of the memory cell transistors M1, M2 . . .
    Type: Grant
    Filed: August 11, 1999
    Date of Patent: May 15, 2001
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Hitoshi Kokubun, Shooji Kitazawa, Keiichiro Takeda, Yuichi Ashizawa
  • Patent number: 5977799
    Abstract: Since the logic levels on both edge sides (node n1 and node n2) of an NMOS connected to a word line are set to the same level corresponding to the logic level of the chip enable signal, even in a memory having an MOS transistor with a short gate length due to an increase of the storage capacity, a leak voltage can be prevented from taking place in the chip standby state.
    Type: Grant
    Filed: April 23, 1996
    Date of Patent: November 2, 1999
    Assignee: OKI Electric Industry Co., Ltd.
    Inventors: Nobuhiro Kai, Hitoshi Kokubun
  • Patent number: 5303798
    Abstract: In a mounting, arrangement for an internal combustion engine with at least one row of cylinders arranged in a longitudinal direction of a four-wheel drive or a front-wheel drive automotive vehicle, which employs a front-wheel drive shaft and a front differential connected to the front-wheel drive shaft, the front-wheel drive shaft and the front differential are both arranged at the side of the engine in the vicinity of the front end of the engine block, and engine mounts for mounting the engine, are arranged rearwardly of the front-wheel drive shaft, so as to assure a shorter entire length and a shorter entire width of the power plant and to provide an optimal car weight balance between front and rear wheels.
    Type: Grant
    Filed: May 26, 1992
    Date of Patent: April 19, 1994
    Assignee: Nissan Motor Co., Ltd.
    Inventors: Kazumi Nakamura, Saburo Yamasaki, Hitoshi Kokubun
  • Patent number: 5181736
    Abstract: A structure of a vehicle includes a cross member which constitutes a part of a vehicle body. A rear suspension unit mounted on the cross member has two front and two rear suspension-supporting insulators and a transverse leaf spring. A spring support member for supporting the transverse leaf spring is secured to the vehicle body and positioned below the cross member. Two rear suspension-supporting bolts have upper end portions secured to the cross member, lower end portions secured to the spring support member, and middle portions secured to the rear suspension-supporting insulators of the rear suspension unit.
    Type: Grant
    Filed: August 5, 1991
    Date of Patent: January 26, 1993
    Assignee: Nissan Motor Co., Ltd.
    Inventor: Hitoshi Kokubun
  • Patent number: 5180929
    Abstract: A voltage measuring circuit for detecting an unknown voltage in a semiconductor integrated circuit or the like. A voltage to be measured is converted into a first current by a current converting transistor, and a difference between the first current and a reference current is converted into a voltage. As a result, the voltage measuring circuit can be arranged without using a floating node, whereby it is possible to prevent variations in a desired voltage value to be measured.
    Type: Grant
    Filed: June 12, 1991
    Date of Patent: January 19, 1993
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Hitoshi Kokubun
  • Patent number: 5148397
    Abstract: A semiconductor memory which is capable of measuring a threshold voltage in a memory cell. The semiconductor memory comprises memory arrays having a plurality of memory cells arranged in a matrix, means for selecting the memory cell, and a sense amplifier for comparing a current flowing through the selected memory cell with a current flowing through a dummy cell and provides an output indicative of a resultant comparison value. The memory cells each include a first switching means having a first transconductance at the time "1" is written in the memory cell and having a second transconductance at the time "0" is written in the memory cell, the value of the second transconductance being greater than the value of the first transconductance. The dummy memory cell includes a second switching means having a third transconductance value of which is in the middle between values of the first and the second transconductance. The memory cells and the dummy cell each have a gate coupled to respective external terminals.
    Type: Grant
    Filed: March 4, 1991
    Date of Patent: September 15, 1992
    Assignee: Oki Electric Industry Co. Ltd.
    Inventor: Hitoshi Kokubun
  • Patent number: 5134384
    Abstract: The data coincidence detecting circuit detects the coincidence of first data having bits with second data having bits. The data conincidence detecting circuit includes input lines, with the bits of the first data being supplied to respectively, a first storing circuit having first storing elements to store the bits of the first data therein and a second storing circuit having second storing elements to store the bits of the second data therein. The first element has first and second terminals and an input terminal connected to the input line through a node. The second element has first and second terminals and is connected to the first element. The first and second elements have a function for electrically connecting between the first and second terminals when the stored bit is a first state and disconnecting between the first and second terminals when the stored bit is a second state.
    Type: Grant
    Filed: February 28, 1990
    Date of Patent: July 28, 1992
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Hitoshi Kokubun
  • Patent number: 4952821
    Abstract: In a voltage detection circuit, a comparison voltage generator includes reference-setting capacitors, each having a first terminal connected to a comparison voltage node, and switching circuits provided in association with the respective reference-setting capacitors, each switching circuit selectively connecting a second terminal of the associated reference setting capacitor either to a first potential node or to a second potential node.
    Type: Grant
    Filed: June 13, 1988
    Date of Patent: August 28, 1990
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Hitoshi Kokubun
  • Patent number: 4664408
    Abstract: A pair of upstanding connecting rods connected to the free ends of a U-shaped stabilizer bar are axially movably supported on respective vehicle body brackets or suspension members. A locking mechanism is provided to prevent axial movement of the connecting rods relative to the vehicle body brackets or suspension members when to make the stabilizer bar effective. A selection mechanism is mechanically connected to the locking mechanism to actuate the same to selectively prevent and allow the above mentioned axial movement of the connecting rods.
    Type: Grant
    Filed: September 30, 1985
    Date of Patent: May 12, 1987
    Assignee: Nissan Motor Co., Ltd.
    Inventors: Masaru Saotome, Fumitaka Saigo, Hitoshi Kokubun