Abstract: A navigation system includes: an intersection enlargement creation unit that creates based upon map data an intersection enlargement over a predetermined map range around a target guidance-requiring intersection present on a recommended route, at which a turn should be made; an intersection enlargement display unit that displays at a display monitor the intersection enlargement having been created by the intersection enlargement creation unit; and a mark display unit that displays an indicator mark indicating an advancing path shape at a next guidance-requiring intersection immediately beyond the target guidance-requiring intersection over the intersection enlargement on display at the display monitor.

Abstract: A navigation system includes: an intersection enlargement creation unit that creates based upon map data an intersection enlargement over a predetermined map range around a target guidance-requiring intersection present on a recommended route, at which a turn should be made; an intersection enlargement display unit that displays at a display monitor the intersection enlargement having been created by the intersection enlargement creation unit; and a mark display unit that displays an indicator mark indicating an advancing path shape at a next guidance-requiring intersection immediately beyond the target guidance-requiring intersection over the intersection enlargement on display at the display monitor.

Abstract: A digital information copying management apparatus includes a data storage unit that is arranged to store data, a data processing unit that controls writing and reading of the data to and from the data storage unit, a bus that connects the data storage unit and the data processing unit for transmitting data having plural bits in parallel, and a logic circuit unit that is provided between the data storage unit and the data processing unit, and that inverts at least one bit data of the data that is transferred in the bus in parallel.

Abstract: A synchronization control apparatus and method enables synchronization control which can flexibly accommodate various frequencies using a simple circuit construction. A storage device that has a predetermined capacity, such as a FIFO, stores externally input data. A CPU controls an output frequency at which data stored in the storage device are output, based on an average frequency which is an average of the output frequency and on a coefficient for setting the average frequency at a fixed value, the first frequency controlling device calculating the average of the output frequency whenever a timing signal is input in accordance with a predetermined cycle and determining the coefficient depending on a free capacity of the storage device at a time of inputting of the timing signal.

Abstract: A digital variable-frequency oscillator has an output frequency thereof variable in dependence upon a frequency control variable. Externally input data are stored in a data storage device, from which the data are generated in accordance with the output of the digital variable-frequency oscillator. A remaining data amount of the data storage device is detected in response to an externally input timing signal that is received in synchronism with the data received by the data storage device such that synchronization is performed based on the timing signal. A filtering operation is performed on values of the frequency control variable so as to calculate an average value of the frequency control variable. A new value of the frequency control variable is calculated based on the calculated average value and the difference between the detected remaining data amount of the data storage device and a target data amount thereof.

Abstract: An electronic apparatus has a processor for processing data, a storage device for storing the data, a controller for controlling the storage device and a data bus. The storage device stores data represented by a set of bits arranged in an order. The controller reads the data from the storage device and writes the data into the storage device during the course of the processing of the data by the processor. The bus connects between the storage device and the controller for transferring of the data therebetween. The bus is structured by a set of paths enabling parallel transferring of the set of the bits. The set of the paths are disarranged between the controller and the storage device such that the order of the bits of the stored set is changed from the order of the bits of the processed set.

Abstract: A synchronization control apparatus and method enables synchronization control which can flexibly accommodate various frequencies using a simple circuit construction. A storage device that has a predetermined capacity, such as a FIFO, stores externally input data. A CPU controls an output frequency at which data stored in the storage device are output, based on an average frequency which is an average of the output frequency and on a coefficient for setting the average frequency at a fixed value, the first frequency controlling device calculating the average of the output frequency whenever a timing signal is input in accordance with a predetermined cycle and determining the coefficient depending on a free capacity of the storage device at a time of inputting of the timing signal.

Abstract: A frequency control apparatus controls the frequency of an output signal thereof in synchronism with an externally input timing signal. A variable frequency oscillator generates the output signal such that the output signal has a frequency thereof variable in response to a control signal input to the variable frequency oscillator. An input device receives the timing signal. A checking device checks a monitor amount variable in response to the frequency of the output signal from the variable frequency oscillator, in timing in which the timing signal is input. A calculating device calculates a difference between the checked monitor amount and a predetermined desired amount. A control device controls the control signal input to the variable frequency oscillator such that the calculated difference becomes zero.