Patents by Inventor Hitoshi Kuribayashi

Hitoshi Kuribayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8080846
    Abstract: A semiconductor device is disclosed which improves the breakdown voltage of a planar-type junction edge terminating structure. The device includes an n-type semiconductor substrate layer common to an active section and an edge terminating section. An n-type drift region is formed selectively on the n-type semiconductor substrate layer in the active section and a p-type partition region is formed selectively on the n-type semiconductor substrate layer in the active section. A p-type base/body region is formed on the n-type drift region and the partition region. A source electrode is connected electrically to the p-type base/body region. A p-type partition region is formed in the edge terminating section between the p-type base/body region and the scribe plane of the semiconductor device such that the p-type partition region in the edge terminating section surrounds the p-type base/body region. A drain electrode is connected electrically to the n-type semiconductor substrate layer.
    Type: Grant
    Filed: June 15, 2007
    Date of Patent: December 20, 2011
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Koh Yoshikawa, Setsuko Wakimoto, Hitoshi Kuribayashi
  • Patent number: 7510975
    Abstract: In the method for manufacturing a semiconductor device according to the invention including the step of forming trenches having the depth thereof in perpendicular to the major surface of a semiconductor substrate, the step of forming trenches includes the steps of performing trench etching using an insulator film, formed on the major surface of the semiconductor substrate and shaped with a predetermined pattern, for a mask to form the trenches; etching the inside of the trenches using a halogen containing gas to smoothen the inside of the trenches; and thermally treating in a non-oxidizing and non-nitriding atmosphere. The manufacturing method according to the invention facilitates well removing the etching residues remaining in the trenches and rounding the trench corners properly when the trenches are 2 ?m or narrower in width and even when the trenches are 1 ?m or narrower in width.
    Type: Grant
    Filed: September 23, 2005
    Date of Patent: March 31, 2009
    Assignee: Fuji Electric Holdings Co., Ltd.
    Inventors: Daisuke Kishimoto, Hitoshi Kuribayashi, Yuji Sano, Akihiko Ohi, Yoshihiko Nagayasu
  • Patent number: 7410873
    Abstract: A method of forming a semiconductor device uses an anneal technique to planarize and round corners of a trench formed in a substrate. The substrate is annealed under a normal pressure in an inert atmosphere, such as an atmosphere containing one of argon, helium, and neon, or an atmosphere of a gas mixture of hydrogen of 4% or less and one of argon, helium, and neon at a temperature of between 900° C. and 1050° C. for a time of between 30 seconds and 30 minutes to round the trench corners and planarize the trench side walls. Alternatively, after removing a mask for forming the trench, the substrate can be annealed in the inert atmosphere. This provides easy and inexpensive way of planarizing the trench side walls, as well as rounding of the trench corners. Moreover, by removing the mask for forming the trench before annealing enables the semiconductor device to have a highly reliable gate insulator film with good reproducibility.
    Type: Grant
    Filed: March 26, 2003
    Date of Patent: August 12, 2008
    Assignee: Fuji Electric Holdings Co., Ltd.
    Inventor: Hitoshi Kuribayashi
  • Patent number: 7368363
    Abstract: A method of manufacturing a semiconductor device includes the steps of: exposing a semiconductor surface of a substrate; annealing the substrate in a hydrogen atmosphere at a hydrogen pressure between 200 Torr and 760 Torr and a temperature between 1000° C. and 1050° C. to planarize the exposed semiconductor surface; and forming a gate insulator film on the planarized semiconductor surface.
    Type: Grant
    Filed: November 8, 2004
    Date of Patent: May 6, 2008
    Assignee: Fuji Electric Device Technology Co., Ltd.
    Inventors: Reiko Hiruta, Hitoshi Kuribayashi, Ryosuke Shimizu
  • Publication number: 20070290267
    Abstract: A semiconductor device is disclosed which improves the breakdown voltage of a planar-type junction edge terminating structure. The device includes an n-type semiconductor substrate layer common to an active section and an edge terminating section. An n-type drift region is formed selectively on the n-type semiconductor substrate layer in the active section and a p-type partition region is formed selectively on the n-type semiconductor substrate layer in the active section. A p-type base/body region is formed on the n-type drift region and the partition region. A source electrode is connected electrically to the p-type base/body region. A p-type partition region is formed in the edge terminating section between the p-type base/body region and the scribe plane of the semiconductor device such that the p-type partition region in the edge terminating section surrounds the p-type base/body region. A drain electrode is connected electrically to the n-type semiconductor substrate layer.
    Type: Application
    Filed: June 15, 2007
    Publication date: December 20, 2007
    Applicant: Fuji Electric Holdings Co., Ltd
    Inventors: Koh Yoshikawa, Setsuko Wakimoto, Hitoshi Kuribayashi
  • Publication number: 20060154438
    Abstract: In the method for manufacturing a semiconductor device according to the invention including the step of forming trenches having the depth thereof in perpendicular to the major surface of a semiconductor substrate, the step of forming trenches includes the steps of performing trench etching using an insulator film, formed on the major surface of the semiconductor substrate and shaped with a predetermined pattern, for a mask to form the trenches; etching the inside of the trenches using a halogen containing gas to smoothen the inside of the trenches; and thermally treating in a non-oxidizing and non-nitriding atmosphere. The manufacturing method according to the invention facilitates well removing the etching residues remaining in the trenches and rounding the trench corners properly when the trenches are 2 ?m or narrower in width and even when the trenches are 1 ?m or narrower in width.
    Type: Application
    Filed: September 23, 2005
    Publication date: July 13, 2006
    Inventors: Daisuke Kishimoto, Hitoshi Kuribayashi, Yuji Sano, Akihiko Ohi, Yoshihiko Nagayasu
  • Publication number: 20050106847
    Abstract: A method of manufacturing a semiconductor device includes the steps of: exposing a semiconductor surface of a substrate; annealing the substrate in a hydrogen atmosphere at a hydrogen pressure between 200 Torr and 760 Torr and a temperature between 1000° C. and 1050° C. to planarize the exposed semiconductor surface; and forming a gate insulator film on the planarized semiconductor surface.
    Type: Application
    Filed: November 8, 2004
    Publication date: May 19, 2005
    Inventors: Reiko Hiruta, Hitoshi Kuribayashi, Ryosuke Shimizu
  • Publication number: 20050106794
    Abstract: A semiconductor substrate is annealed after forming a trench in a semiconductor substrate and prior to forming a gate insulator film, at an annealing temperature T between 980° C. and 1150° C. in an atmosphere of a gas mixture containing a rare gas and hydrogen, in which the content of hydrogen is 1.3×10?18 exp(0.043T) % or lower in volume, to planarize the side wall of the trench and to round the corners of the trench at the curvature of 0.003 nm?1 or smaller. Alternatively, a semiconductor substrate with a trench formed therein is annealed prior to forming a gate insulator film, at an annealing temperature T between 980° C. and 1040° C. in an atmosphere of a gas mixture containing a rare gas and hydrogen, in which the content of hydrogen is 6.11×10?14 exp(0.0337T) % or higher in volume, to planarize the side wall of the trench but so as not to round the corners of the trench such that the curvature thereof is 0.006 nm?1 or higher.
    Type: Application
    Filed: September 20, 2004
    Publication date: May 19, 2005
    Inventors: Hitoshi Kuribayashi, Reiko Hiruta, Ryosuke Shimizu
  • Publication number: 20030219948
    Abstract: A method of forming a semiconductor device uses an anneal technique to planarize and round corners of a trench formed in a substrate. The substrate is annealed under a normal pressure in an inert atmosphere, such as an atmosphere containing one of argon, helium, and neon, or an atmosphere of a gas mixture of hydrogen of 4% or less and one of argon, helium, and neon at a temperature of between 900° C. and 1050° C. for a time of between 30 seconds and 30 minutes to round the trench corners and planarize the trench side walls. Alternatively, after removing a mask for forming the trench, the substrate can be annealed in the inert atmosphere. This provides easy and inexpensive way of planarizing the trench side walls, as well as rounding of the trench corners. Moreover, by removing the mask for forming the trench before annealing enables the semiconductor device to have a highly reliable gate insulator film with good reproducibility.
    Type: Application
    Filed: March 26, 2003
    Publication date: November 27, 2003
    Inventor: Hitoshi Kuribayashi