Abstract: A data processing device includes a cache memory, a load buffer primary (LBP) for storing 1-line instruction data including an instruction requested to be transmitted by an instruction processing unit and transmitted from a main storage or a secondary cache memory, and a load buffer secondary (LBS) for storing 1-line instruction data preceded by the above described 1-line data. With this configuration, the device may determine the validity of prefetched data in the LBP using lower order bits of the addresses of the data. If the data are determined to be valid, the data stored in the LBS are stored in the cache memory. A cache storage device, hierarchically provided between a central processing unit a n d a main storage device, includes a cache memory, a storage buffer, a write-in buffer and a cache storage control unit. The cache storage device fast writes storage data into a write-in buffer instead of directly into cache memory.

Abstract: In a method and apparatus for address translation for translating a 64-bit virtual address into a real address, the 64-bit virtual address comprises a segment number, a page index and a page offset. When this virtual address is translated into a real address, high order bits of the segment number are first input to a hash generation circuit to obtain a hash address of a link table, and this link table is retrieved by an address obtained by adding lower order bits of the segment number as an offset to obtain tag information of the virtual address and a base address of a page table. Next, the tag information of the virtual address obtained in this manner is compared with the original segment number, and the base address of the page table is judged as correct when they coincide with each other.