Patents by Inventor Hitoshi Negishi

Hitoshi Negishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6627473
    Abstract: A high electron mobility transitor has a channel layer overlain by an electron supply layer held in contact with a gate electrode, and source/drain electrodes form ohmic contact together with cap layers, and resistive etching stopper are inserted between the cap layers and the electron supply layers for preventing the electron supply layer from over-etching, wherein extremely thin delta-doped layers are formed between the etching stopper layers and the electron supply layer so that the resistance between the electron supply layer and the source/drain electrodes are reduced.
    Type: Grant
    Filed: November 14, 2000
    Date of Patent: September 30, 2003
    Assignee: NEC Compound Semiconductor Devices, Ltd.
    Inventors: Hirokazu Oikawa, Hitoshi Negishi
  • Publication number: 20020187623
    Abstract: A high electron mobility transistor has a channel layer overlain by an electron supply layer held in contact with a gate electrode, and source/drain electrodes form ohmic contact together with cap layers, and resistive etching stopper are inserted between the cap layers and the electron supply layers for preventing the electron supply layer from over-etching, wherein extremely thin delta-doped layers are formed between the etching stopper layers and the electron supply layer so that the resistance between the electron supply layer and the source/drain electrodes are reduced.
    Type: Application
    Filed: July 10, 2002
    Publication date: December 12, 2002
    Applicant: NEC Corporation
    Inventors: Hirokazu Oikawa, Hitoshi Negishi
  • Patent number: 6100555
    Abstract: A recess is made in the semiconductor substrate. A gate electrode has a sectional shape of "T" to have a head overhanging portion and is made in the recess. The gate electrode having a head overhanging portion. A capacitance film is formed under the head overhanging portion of the gate electrode. An ohmic electrode is formed on the semiconductor substrate and at both sides of the gate electrode. In the device, the capacitance film is made of a photosensitive organic film having a smaller permittivity than that of silicon oxide films. This semiconductor device has a small gate parasitic capacitance and the variation in the capacitance can be reduced.
    Type: Grant
    Filed: November 2, 1999
    Date of Patent: August 8, 2000
    Assignee: NEC Corporation
    Inventor: Hitoshi Negishi
  • Patent number: 6099640
    Abstract: A method of promoting evaporation of excess indium from a surface of an indium containing compound semiconductor single crystal layer during a discontinuation of a molecular beam epitaxial growth. Substantial supply of all elements for the indium containing compound semiconductor single crystal layer are stopped at least until a substrate temperature rises to a predetermined temperature of not less than an indium re-evaporation initiation temperature.
    Type: Grant
    Filed: September 3, 1998
    Date of Patent: August 8, 2000
    Assignee: NEC Corporation
    Inventor: Hitoshi Negishi
  • Patent number: 5635759
    Abstract: A semiconductor device includes a base case 12, a first conductive pattern 6 selectively formed on the base case 12 a semiconductor element 1 mounted on the first pattern 6, a second conductive pattern 7 selectively formed on the base case 12 and connected to a first electrode 2 of the semiconductor element 1, the second conductive pattern 7 being separated from the first conductive pattern 6 to form a first parasitic capacitance therebetween, and a third conductive pattern 8 selectively formed on the base case 12 and connected to a second electrode 3 of the semiconductor element 1, the third conductive pattern 8 being separated from the first conductive pattern 6 to form a second parasitic capacitance therebetween, the first parasitic capacitance being larger than the second parasitic capacitance.
    Type: Grant
    Filed: November 13, 1995
    Date of Patent: June 3, 1997
    Assignee: NEC Corporation
    Inventor: Hitoshi Negishi