Abstract: A particle size distribution measurement device includes a cell holding body 31 that holds a measurement cell 2 containing a measurement sample and a dispersion medium and a reference cell 6 containing a reference sample and is rotated by a motor 322, and a cell discrimination mechanism 7 that discriminates the cells 2, 6 passing through a predetermined rotation position by using a magnetic force or electrostatic capacitance.

Abstract: According to one embodiment, a semiconductor integrated circuit includes a semiconductor integrated circuit a voltage regulator providing a prescribed power-supply voltage, a plurality of delay test circuits, each of the delay test circuits being configured in each of areas where electrical current flows in response to each of operation modes, a test control unit executing a delay test using the delay test circuit under a test mode while decreasing a power-supply voltage in a stepwise fashion, a supply voltage decision unit deciding the power-supply voltage of the operation mode on a basis of the delay test, a memory unit storing the power-supply voltage of each operation mode, a supply voltage configuration unit reading out the power-supply voltage corresponding to the operation mode from the memory unit, and the supply configuration unit arranging the power-supply voltage as an output voltage of the voltage regulator when each of the operation modes starts to execute.

Abstract: According to one embodiment, a semiconductor integrated circuit includes a semiconductor integrated circuit a voltage regulator providing a prescribed power-supply voltage, a plurality of delay test circuits, each of the delay test circuits being configured in each of areas where electrical current flows in response to each of operation modes, a test control unit executing a delay test using the delay test circuit under a test mode while decreasing a power-supply voltage in a stepwise fashion, a supply voltage decision unit deciding the power-supply voltage of the operation mode on a basis of the delay test, a memory unit storing the power-supply voltage of each operation mode, a supply voltage configuration unit reading out the power-supply voltage corresponding to the operation mode from the memory unit, and the supply configuration unit arranging the power-supply voltage as an output voltage of the voltage regulator when each of the operation modes starts to execute.

Abstract: A normal bus and an extension bus having the same bit width as the normal bus are provided. A line buffer has a plurality of line regions to store pixel data of input image data. A line buffer writing control portion controls a direction in which the pixel data is to be written to the line buffer. A line buffer reading control portion reads out the pixel data stored in the line buffer and to output the read out pixel data to the buses selectively. A frame memory writing control portion controls a destination in a frame memory to which the pixel data obtained from the buses is to be written. An address control portion controls a writing address in the frame memory. The line buffer writing control portion controls the writing direction in the line buffer in accordance with an image rotation command signal.