Abstract: The vehicle controller controls a vehicle. The vehicle includes a transmission and an internal combustion engine that has a variable valve actuation device. The vehicle controller includes an execution device. The execution device executes first and second gear ratio adjustment processes and first and second intake VVT adjustment processes. The first intake VVT adjustment process includes adjusting the intake valve timing such that the internal combustion engine is operated in an Atkinson cycle. The second intake VVT adjustment process includes setting the intake valve timing such that the closing timing of the intake valve is more advanced than in a case in which the first intake VVT adjustment process is executed.

Abstract: Transmitters for data communication can include a pattern generator configured to generate parallel data stream composed of k bits, k being a natural number greater than 2, a serializer configured to convert the parallel data stream into a serial data stream, a pre-emphasis circuit configured to pre-emphasize the serial data stream based on a pre-emphasis control value, to transmit the pre-emphasized serial data stream to a receiver via a first transmission line, and a pre-emphasis controller configured to receive measured values of transmission errors of the pre-emphasized serial data stream from the receiver via a second transmission line, and configured to set the pre-emphasis control value corresponding to a minimum measured value of the transmission errors, to an optimum pre-emphasis control value.

Abstract: A receiver with an equalizer and an equalizing method are disclosed. The method includes equalizing received serial data in the equalizer, detecting an error in equalized serial data output by the equalizer, and determining reset of the equalizer in relation to an error detection.

Abstract: A clock and data recovery (CDR) circuit includes a sampler, a CDR loop and a phase interpolator. The sampler samples serial data in response to a recovery clock signal to generate a serial sampling pulse. The CDR loop transforms the serial sampling pulse into parallel data, generates a plurality of phase signals with a first speed based on the parallel data, and generates a phase control signal with a second speed higher than the first speed based on the plurality of phase signals. The phase interpolator generates the recovery clock signal by controlling a phase of a reference clock signal in response to the phase control signal. Therefore, the CDR circuit may recover data and a clock with a relatively high speed.

Abstract: A differential driver includes first and second pull-up resistors respectively connected to first and second output terminals, a plurality of differential-input transistor pairs connected each to the first and second output terminals, current sources connected each to the differential-input transistor pairs, and a slew rate controller adapted to generate differential input signals to be applied each to the differential-input transistor pairs in response to an input signal. The slew rate controller may output the differential input signals simultaneously or sequentially.

Abstract: A circuit for measuring an eye size generates first sampled data by sampling received data with recovered clock signals and generates second sampled data by sampling the received data with shifted clock signals, in which the recovered clock signals, having different phases, are recovered from the received data. The shifted clock signals are obtained by shifting each phase of at least one of recovered clock signals by respectively predetermined phases. The circuit generates error counts for calculating the eye size of the received data by comparing the first sampled data and the second sampled data and measures the eye size by obtaining a phase range where the error counts are equal to zero. Therefore, the circuit may measure the eye size without interference of frequency offsets and/or jitter of the received data.

Abstract: A deserializer and method for deserializing data are disclosed. The method includes converting data from a serial data domain to a parallel data domain, detecting a comma related to the parallel data while the data is in the serial data domain, wherein conversion of the data from the serial data domain to the parallel data domain is made in relation to detection of the comma.

Abstract: Transmitters for data communication can include a pattern generator configured to generate parallel data stream composed of k bits, k being a natural number greater than 2, a serializer configured to convert the parallel data stream into a serial data stream, a pre-emphasis circuit configured to pre-emphasize the serial data stream based on a pre-emphasis control value, to transmit the pre-emphasized serial data stream to a receiver via a first transmission line, and a pre-emphasis controller configured to receive measured values of transmission errors of the pre-emphasized serial data stream from the receiver via a second transmission line, and configured to set the pre-emphasis control value corresponding to a minimum measured value of the transmission errors, to an optimum pre-emphasis control value.

Abstract: Transceivers for data communications can include a first transmission line, a transmitter configured to transmit a first serial data stream that is obtained by deserializing first parallel data composed of k bits via the first transmission line, k being a natural number greater than 2, a second transmission line, and a receiver configured to measure transmission errors of a second serial data stream received through the first transmission line to transmit the measured transmission errors to the transmitter via the second transmission line and wherein the transmitter comprises a pattern generator configured to generate the first parallel data, a serializer configured to serialize the first parallel data to the first serial data, a pre-emphasis circuit configured to pre-emphasize the first serial data stream based on a pre-emphasis control value to transmit the pre-emphasized serial data to the receiver via the first transmission line, and a pre-emphasis controller configured to receive the transmission errors

Abstract: A method of transmitting data can include pre-emphasizing data for transmission by a transmitter over a transmission line based on an error feedback signal provided to the transmitter from a receiver of the pre-emphasized data.

Abstract: A clock recovery system includes a sampler that is configured to sample an input data signal in synchronization with a modulated clock signal to generate a sample of the input data signal. A phase comparator is configured to compute a position of a transition edge of the input data signal using the sample data signal, and to compare the computed position with a position of an edge of the modulated clock signal to generate a comparison result. An edge counter is configured to count transition edges of the sample data signal. A controller is configured to generate first and second control signals based on the comparison result and the count of the transition edges. A clock phase modulator is configured to generate the modulated clock signal by adjusting a phase of an input clock signal responsive to the first and second control signals, such that the phase is increased in response to the first control signal and reduced in response to the second control signal.

Abstract: An output buffer circuit includes: a differential circuit; and first and second load circuits coupled between the differential circuit and a high power supply voltage VDDH. Such a differential circuit includes first and second NMOS transistors having low-voltage gate dielectric layers susceptible to deterioration at operation above a maximum gate-body voltage VgbMAX (where VDDH>VgbMAX), respectively. Body electrodes & source electrodes are coupled to a common node. Gate electrodes are coupled to first and second differential input signals, respectively, such that voltages on drains of the first and second NMOS transistors represent results of a differential switching operation, respectively. More particularly, the drains of the first and second NMOS transistors are coupled to the first and second loads. The common node is coupled to a bias voltage such that Vgb of the first & second NMOS transistors is VgbMAX?Vgb.

Abstract: A receiver with an equalizer and an equalizing method are disclosed. The method includes equalizing received serial data in the equalizer, detecting an error in equalized serial data output by the equalizer, and determining reset of the equalizer in relation to an error detection.

Abstract: A deserializer and method for deserializing data are disclosed. The method includes converting data from a serial data domain to a parallel data domain, detecting a comma related to the parallel data while the data is in the serial data domain, wherein conversion of the data from the serial data domain to the parallel data domain is made in relation to detection of the comma.

Abstract: A differential driver includes first and second pull-up resistors respectively connected to first and second output terminals, a plurality of differential-input transistor pairs connected each to the first and second output terminals, current sources connected each to the differential-input transistor pairs, and a slew rate controller adapted to generate differential input signals to be applied each to the differential-input transistor pairs in response to an input signal. The slew rate controller may output the differential input signals simultaneously or sequentially.

Abstract: A clock and data recovery (CDR) circuit includes a sampler, a CDR loop and a phase interpolator. The sampler samples serial data in response to a recovery clock signal to generate a serial sampling pulse. The CDR loop transforms the serial sampling pulse into parallel data, generates a plurality of phase signals with a first speed based on the parallel data, and generates a phase control signal with a second speed higher than the first speed based on the plurality of phase signals. The phase interpolator generates the recovery clock signal by controlling a phase of a reference clock signal in response to the phase control signal. Therefore, the CDR circuit may recover data and a clock with a relatively high speed.

Abstract: A circuit for measuring an eye size generates first sampled data by sampling received data with recovered clock signals and generates second sampled data by sampling the received data with shifted clock signals, in which the recovered clock signals, having different phases, are recovered from the received data. The shifted clock signals are obtained by shifting each phase of at least one of recovered clock signals by respectively predetermined phases. The circuit generates error counts for calculating the eye size of the received data by comparing the first sampled data and the second sampled data and measures the eye size by obtaining a phase range where the error counts are equal to zero. Therefore, the circuit may measure the eye size without interference of frequency offsets and/or jitter of the received data.

Abstract: An output buffer circuit includes: a differential circuit; and first and second load circuits coupled between the differential circuit and a high power supply voltage VDDH. Such a differential circuit includes first and second NMOS transistors having low-voltage gate dielectric layers susceptible to deterioration at operation above a maximum gate-body voltage VgbMAX (where VDDH>VgbMAX), respectively. Body electrodes & source electrodes are coupled to a common node. Gate electrodes are coupled to first and second differential input signals, respectively, such that voltages on drains of the first and second NMOS transistors represent results of a differential switching operation, respectively. More particularly, the drains of the first and second NMOS transistors are coupled to the first and second loads. The common node is coupled to a bias voltage such that Vgb of the first & second NMOS transistors is VgbMAX?Vgb.

Abstract: A clock recovery system includes a sampler that is configured to sample an input data signal in synchronization with a modulated clock signal to generate a sample of the input data signal. A phase comparator is configured to compute a position of a transition edge of the input data signal using the sample data signal, and to compare the computed position with a position of an edge of the modulated clock signal to generate a comparison result. An edge counter is configured to count transition edges of the sample data signal. A controller is configured to generate first and second control signals based on the comparison result and the count of the transition edges. A clock phase modulator is configured to generate the modulated clock signal by adjusting a phase of an input clock signal responsive to the first and second control signals, such that the phase is increased in response to the first control signal and reduced in response to the second control signal.

Abstract: A method of transmitting data can include pre-emphasizing data for transmission by a transmitter over a transmission line based on an error feedback signal provided to the transmitter from a receiver of the pre-emphasized data.