Patents by Inventor Hitoshi Okano
Hitoshi Okano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11961783Abstract: To provide a semiconductor apparatus that makes it possible to further improve the efficiency in heat dissipation, and to provide an electronic apparatus that includes the semiconductor apparatus. A semiconductor apparatus is provided that includes a substrate, a plurality of chips each stacked on the substrate, and a plurality of guard rings each formed on an outer peripheral portion of a corresponding one of the plurality of chips to surround the corresponding one of the plurality of chips, in which at least portions of at least two of the plurality of guard rings are connected to each other through a thermally conductive material. Further, an electric apparatus is provided that includes the semiconductor apparatus.Type: GrantFiled: February 7, 2020Date of Patent: April 16, 2024Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventor: Hitoshi Okano
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Patent number: 11810851Abstract: The present technology relates to a semiconductor device in which a MIM capacitive element can be formed without any process damage, and a method for manufacturing the semiconductor device. In a semiconductor device, wiring layers of a first multilayer wiring layer formed on a first semiconductor substrate and a second multilayer wiring layer formed on a second semiconductor substrate are bonded to each other by wafer bonding. The semiconductor device includes a capacitive element including an upper electrode, a lower electrode, and a capacitive insulating film between the upper electrode and the lower electrode. One electrode of the upper electrode and the lower electrode is formed with a first conductive layer of the first multilayer wiring layer and a second conductive layer of the second multilayer wiring layer. The present technology can be applied to a semiconductor device or the like formed by joining two semiconductor substrates, for example.Type: GrantFiled: February 28, 2022Date of Patent: November 7, 2023Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Hitoshi Okano, Hiroyuki Kawashima
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Publication number: 20230095332Abstract: The present technology relates to an imaging element and a semiconductor chip that can implement a low height of the imaging element. A first chip including a photo diode; and a second chip including a circuit processing a signal transmitted from the photo diode are stacked, and a charging film is disposed on a second face of the second chip that is on a side opposite to a first face on which the first chip is stacked. The charging film is disposed in a part or the entirety of the second face. For example, the present technology can be applied to an imaging element, in which a plurality of chips are configured to be stacked, that can implement a low height and a small size.Type: ApplicationFiled: March 3, 2021Publication date: March 30, 2023Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Hitoshi OKANO, Kan SHIMIZU
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Publication number: 20220302020Abstract: The present technology relates to a semiconductor device in which a MIM capacitive element can be formed without any process damage, and a method for manufacturing the semiconductor device. In a semiconductor device, wiring layers of a first multilayer wiring layer formed on a first semiconductor substrate and a second multilayer wiring layer formed on a second semiconductor substrate are bonded to each other by wafer bonding. The semiconductor device includes a capacitive element including an upper electrode, a lower electrode, and a capacitive insulating film between the upper electrode and the lower electrode. One electrode of the upper electrode and the lower electrode is formed with a first conductive layer of the first multilayer wiring layer and a second conductive layer of the second multilayer wiring layer. The present technology can be applied to a semiconductor device or the like formed by joining two semiconductor substrates, for example.Type: ApplicationFiled: February 28, 2022Publication date: September 22, 2022Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Hitoshi OKANO, Hiroyuki KAWASHIMA
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Patent number: 11380804Abstract: A semiconductor device including a first conductivity-type layer into which first conductivity-type impurities are introduced, a second conductivity-type layer into which second conductivity-type impurities are introduced, the second conductivity-type impurities being different in polarity from the first conductivity-type impurities, and an intermediate layer that is sandwiched between the first conductivity-type layer and the second conductivity-type layer, and does not include the first conductivity-type impurities or the second conductivity-type impurities, or includes the first conductivity-type impurities or the second conductivity-type impurities at a concentration lower than a concentration of the first conductivity-type impurities in the first conductivity-type layer or the second conductivity-type impurities in the second conductivity-type layer, the first conductivity-type layer, the intermediate layer, and the second conductivity-type layer being stacked in a thickness direction of a semiconductorType: GrantFiled: July 13, 2018Date of Patent: July 5, 2022Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventor: Hitoshi Okano
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Publication number: 20220208642Abstract: To provide a semiconductor apparatus that makes it possible to further improve the efficiency in heat dissipation, and to provide an electronic apparatus that includes the semiconductor apparatus. A semiconductor apparatus is provided that includes a substrate, a plurality of chips each stacked on the substrate, and a plurality of guard rings each formed on an outer peripheral portion of a corresponding one of the plurality of chips to surround the corresponding one of the plurality of chips, in which at least portions of at least two of the plurality of guard rings are connected to each other through a thermally conductive material. Further, an electric apparatus is provided that includes the semiconductor apparatus.Type: ApplicationFiled: February 7, 2020Publication date: June 30, 2022Inventor: HITOSHI OKANO
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Patent number: 11296020Abstract: The present technology relates to a semiconductor device in which a MIM capacitive element can be formed without any process damage, and a method for manufacturing the semiconductor device. In a semiconductor device, wiring layers of a first multilayer wiring layer formed on a first semiconductor substrate and a second multilayer wiring layer formed on a second semiconductor substrate are bonded to each other by wafer bonding. The semiconductor device includes a capacitive element including an upper electrode, a lower electrode, and a capacitive insulating film between the upper electrode and the lower electrode. One electrode of the upper electrode and the lower electrode is formed with a first conductive layer of the first multilayer wiring layer and a second conductive layer of the second multilayer wiring layer. The present technology can be applied to a semiconductor device or the like formed by joining two semiconductor substrates, for example.Type: GrantFiled: December 7, 2018Date of Patent: April 5, 2022Assignee: Sony Semiconductor Solutions CorporationInventors: Hitoshi Okano, Hiroyuki Kawashima
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Publication number: 20210090987Abstract: The present technology relates to a semiconductor device in which a MIM capacitive element can be formed without any process damage, and a method for manufacturing the semiconductor device. In a semiconductor device, wiring layers of a first multilayer wiring layer formed on a first semiconductor substrate and a second multilayer wiring layer formed on a second semiconductor substrate are bonded to each other by wafer bonding. The semiconductor device includes a capacitive element including an upper electrode, a lower electrode, and a capacitive insulating film between the upper electrode and the lower electrode. One electrode of the upper electrode and the lower electrode is formed with a first conductive layer of the first multilayer wiring layer and a second conductive layer of the second multilayer wiring layer. The present technology can be applied to a semiconductor device or the like formed by joining two semiconductor substrates, for example.Type: ApplicationFiled: December 7, 2018Publication date: March 25, 2021Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Hitoshi OKANO, Hiroyuki KAWASHIMA
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Publication number: 20200357933Abstract: [Problem] Provided is a semiconductor device that is allowed to withstand a higher voltage while having a more efficient occupancy area.Type: ApplicationFiled: July 13, 2018Publication date: November 12, 2020Inventor: HITOSHI OKANO
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Patent number: 9917091Abstract: A method of manufacturing a semiconductor device, includes: forming an insulating film on a first surface of a semiconductor substrate; and forming a hydrogen supply film on a second surface facing the first surface of the semiconductor substrate, the hydrogen supply film containing one or more of silicon oxide, TEOS, BPSG, BSG, PSG, FSG, carbon-containing silicon oxide, silicon nitride, carbon-containing silicon nitride, and oxygen-containing silicon carbide.Type: GrantFiled: May 28, 2015Date of Patent: March 13, 2018Assignee: SONY CORPORATIONInventors: Katsuhisa Kugimiya, Kenichi Murata, Hitoshi Okano, Shigetaka Mori, Hiroyuki Kawashima, Takuma Matsuno
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Publication number: 20170207223Abstract: A method of manufacturing a semiconductor device, includes: forming an insulating film on a first surface of a semiconductor substrate; and forming a hydrogen supply film on a second surface facing the first surface of the semiconductor substrate, the hydrogen supply film containing one or more of silicon oxide, TEOS, BPSG, BSG, PSG, FSG, carbon-containing silicon oxide, silicon nitride, carbon-containing silicon nitride, and oxygen-containing silicon carbide.Type: ApplicationFiled: May 28, 2015Publication date: July 20, 2017Inventors: KATSUHISA KUGIMIYA, KENICHI MURATA, HITOSHI OKANO, SHIGETAKA MORI, HIROYUKI KAWASHIMA, TAKUMA MATSUNO
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Patent number: 5305028Abstract: A multifocal lens has a main lens with a far vision surface refracting power sphere (F) and a near vision sphere (N) and a progressive focal area (P) or an intermediate vision sphere (I), a progressive focal point (P) and a near vision sphere (N) on a segment thereof for giving additional refracting power by surface refracting, in which case the segment projects from the main lens, or refractive index, in which case the segment is embedded in the main lens. A separately produced segment can also be stuck to the surface of the main lens, in which case a series of prism segments can be prepared in advance to select an optimum segment from the series of prism segments according to a prescription.Type: GrantFiled: June 9, 1993Date of Patent: April 19, 1994Inventor: Hitoshi Okano