Patents by Inventor Hitoshi Shiraishi
Hitoshi Shiraishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10058806Abstract: A ballast water treatment device including a cylindrical filter (2) that is disposed in a casing (1) and filters and externally discharges ballast water having flowed inside, comprising: a filter rotating unit (3) that rotates the filter (2) around a shaft center of the filter (2); a suction nozzle (4) that is disposed on the primary side of the filter (2) and opens toward the inner circumferential surface of the filter (2); a waste rinsing water discharging unit (5) that externally discharges waste rinsing water sucked by the suction nozzle (4) from the casing (1); a high-pressure fluid jet nozzle (40) that is disposed on the secondary side of the filter (2), opens toward the outer circumferential surface of the filter (2), and jets high-pressure fluid toward the filter (2); and a high-pressure fluid supplying unit (41) that supplies high-pressure fluid to the high-pressure fluid jet nozzle (40).Type: GrantFiled: November 7, 2013Date of Patent: August 28, 2018Assignee: MIURA CO., LTD.Inventors: Tomoaki Tange, Akinori Kawakami, Hitoshi Shiraishi, Yasutomo Zenman, Yasuhiko Saito, Takamichi Ide
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Publication number: 20160236122Abstract: A ballast water treatment device including a cylindrical filter (2) that is disposed in a casing (1) and filters and externally discharges ballast water having flowed inside, comprising: a filter rotating unit (3) that rotates the filter (2) around a shaft center of the filter (2); a suction nozzle (4) that is disposed on the primary side of the filter (2) and opens toward the inner circumferential surface of the filter (2); a waste rinsing water discharging unit (5) that externally discharges waste rinsing water sucked by the suction nozzle (4) from the casing (1); a high-pressure fluid jet nozzle (40) that is disposed on the secondary side of the filter (2), opens toward the outer circumferential surface of the filter (2), and jets high-pressure fluid toward the filter (2); and a high-pressure fluid supplying unit (41) that supplies high-pressure fluid to the high-pressure fluid jet nozzle (40).Type: ApplicationFiled: November 7, 2013Publication date: August 18, 2016Applicant: MIURA CO., LTD.Inventors: Tomoaki TANGE, Akinori KAWAKAMI, Hitoshi SHIRAISHI, Yasutomo ZENMAN, Yasuhiko SAITO, Takamichi IDE
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Patent number: 7781837Abstract: A method for forming a pattern of a stacked film, includes steps (a) to (e). The step (a) is forming sequentially a first base insulating film and a light shielding material on a transparent substrate. The step (b) is patterning the light shielding material to obtain a light shielding film with a first pattern. The step (c) is forming sequentially a second base insulating film, a semiconductor film and a first oxide film on a substrate. The step (d) is forming a resist pattern with a second pattern on the first oxide film. The step (e) is forming a pattern of a stacked film by dry etching the first oxide film and the semiconductor film, above the light shielding film. The stacked film includes the semiconductor film and the first oxide film. The dry etching includes an etching by using an etching gas and the resist pattern as a mask. The semiconductor film includes a taper angle which is controlled to be within predetermined range.Type: GrantFiled: October 23, 2007Date of Patent: August 24, 2010Assignee: NEC CorporationInventors: Nobuya Seko, Hitoshi Shiraishi, Kenichi Hayashi, Naoto Hirano, Atsushi Yamamoto
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Publication number: 20100025685Abstract: A method of forming a contact hole in an insulating film coating amorphous Si having an irregular surface formed on an insulating substrate, for connecting the amorphous Si to a conductor film formed on the insulating film includes etching the insulating film using reactive ion etching to a depth whereat the irregularity does not disappear, and sputter-etching by physically colliding Ar radicals produced by Ar gas plasma discharge onto the surface of the amorphous Si.Type: ApplicationFiled: September 24, 2009Publication date: February 4, 2010Applicant: NEC CORPORATIONInventor: Hitoshi Shiraishi
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Patent number: 7618898Abstract: A method of forming a contact hole in an insulating film coating amorphous Si having an irregular surface formed on an insulating substrate, for connecting the amorphous Si to a conductor film formed on the insulating film, including: etching the insulating film using reactive ion etching to a depth whereat said irregularity does not disappear; and sputter-etching the surface of the amorphous Si.Type: GrantFiled: March 30, 2005Date of Patent: November 17, 2009Assignee: NEC CorporationInventor: Hitoshi Shiraishi
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Publication number: 20080070414Abstract: A bias correction level can be defined with an improved efficiency when a transfer pattern of a hole is formed, so that the hole can be stably formed as originally designed. When a hole pattern is formed over a substrate, correction reference holes 103 existing in a region 113, which is capable of affecting a formation of a correction target hole 101, is extracted, and a bias correction level employed in the formation of the correction target hole 101 is defined, in accordance with a two-dimensional arrangement of the extracted correction reference holes 103.Type: ApplicationFiled: September 18, 2007Publication date: March 20, 2008Applicant: NEC ELECTRONICS CORPORATIONInventor: Hitoshi SHIRAISHI
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Publication number: 20080048264Abstract: A method for forming a pattern of a stacked film, includes steps (a) to (e). The step (a) is forming sequentially a first base insulating film and a light shielding material on a transparent substrate. The step (b) is patterning the light shielding material to obtain a light shielding film with a first pattern. The step (c) is forming sequentially a second base insulating film, a semiconductor film and a first oxide film on a substrate. The step (d) is forming a resist pattern with a second pattern on the first oxide film. The step (e) is forming a pattern of a stacked film by dry etching the first oxide film and the semiconductor film, above the light shielding film. The stacked film includes the semiconductor film and the first oxide film. The dry etching includes an etching by using an etching gas and the resist pattern as a mask. The semiconductor film includes a taper angle which is controlled to be within predetermined range.Type: ApplicationFiled: October 23, 2007Publication date: February 28, 2008Applicant: NEC CorporationInventors: Nobuya Seko, Hitoshi Shiraishi, Kenichi Hayashi, Naoto Hirano, Atsushi Yamamoto
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Patent number: 7317227Abstract: A semiconductor film serving as an active region of a thin film transistor and an upper oxide film protecting the semiconductor film are dry etched to form the active region. In this case, a fluorine-based gas is used as the etching gas, and the etching gas is switched from the fluorine-based gas to a chlorine-based gas at a point of time when a lower oxide film as an underlying film of the semiconductor film is exposed. As the fluorine-based gas, a mixed gas of CF4 and O2 is used, and suitably, a gas ratio of CF4 and O2 in the mixture gas is set at 1:1, and the dry etching is performed therefor. By this etching, a side face of a two-layer structure of the semiconductor film and upper oxide film is optimally tapered, and a crack or a disconnection is prevented from being occurring in a film crossing over the two-layer structure.Type: GrantFiled: May 28, 2004Date of Patent: January 8, 2008Assignee: NEC CorporationInventors: Hitoshi Shiraishi, Kenichi Hayashi, Naoto Hirano, Atsushi Yamamoto
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Patent number: 7303945Abstract: A method for forming a pattern of a stacked film, includes steps (a) to (e). The step (a) is forming sequentially a first base insulating film and a light shielding material on a transparent substrate. The step (b) is patterning the light shielding material to obtain a light shielding film with a first pattern. The step (c) is forming sequentially a second base insulating film, a semiconductor film and a first oxide film on a substrate. The step (d) is forming a resist pattern with a second pattern on the first oxide film. The step (e) is forming a pattern of a stacked film by dry etching the first oxide film and the semiconductor film, above the light shielding film. The stacked film includes the semiconductor film and the first oxide film. The dry etching includes an etching by using an etching gas and the resist pattern as a mask. The semiconductor film includes a taper angle which is controlled to be within predetermined range.Type: GrantFiled: November 30, 2004Date of Patent: December 4, 2007Assignee: NEC CorporationInventors: Nobuya Seko, Hitoshi Shiraishi, Kenichi Hayashi, Naoto Hirano, Atsushi Yamamoto
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Publication number: 20050221614Abstract: A method of forming a contact hole in an insulating film coating amorphous Si having an irregular surface formed on an insulating substrate, for connecting the amorphous Si to a conductor film formed on the insulating film, including: etching the insulating film using reactive ion etching to a depth whereat said irregularity does not disappear; and sputter-etching the surface of the amorphous Si.Type: ApplicationFiled: March 30, 2005Publication date: October 6, 2005Applicant: NEC CorporationInventor: Hitoshi Shiraishi
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Patent number: 6933241Abstract: A semiconductor film serving as an active region of a thin film transistor and an upper oxide film protecting the semiconductor film are dry etched to form the active region. In this case, a fluorine-based gas is used as the etching gas, and the etching gas is switched from the fluorine-based gas to a chlorine-based gas at a point of time when a lower oxide film as an underlying film of the semiconductor film is exposed. As the fluorine-based gas, a mixed gas of CF4 and O2 is used, and suitably, a gas ratio of CF4 and O2 in the mixture gas is set at 1:1, and the dry etching is performed therefor. By this etching, a side face of a two-layer structure of the semiconductor film and upper oxide film is optimally tapered, and a crack or a disconnection is prevented from being occurring in a film crossing over the two-layer structure.Type: GrantFiled: May 29, 2003Date of Patent: August 23, 2005Assignee: NEC CorporationInventors: Hitoshi Shiraishi, Kenichi Hayashi, Naoto Hirano, Atsushi Yamamoto
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Publication number: 20050156239Abstract: A method for forming a pattern of a stacked film, includes steps (a) to (e). The step (a) is forming sequentially a first base insulating film and a light shielding material on a transparent substrate. The step (b) is patterning the light shielding material to obtain a light shielding film with a first pattern. The step (c) is forming sequentially a second base insulating film, a semiconductor film and a first oxide film on a substrate. The step (d) is forming a resist pattern with a second pattern on the first oxide film. The step (e) is forming a pattern of a stacked film by dry etching the first oxide film and the semiconductor film, above the light shielding film. The stacked film includes the semiconductor film and the first oxide film. The dry etching includes an etching by using an etching gas and the resist pattern as a mask. The semiconductor film includes a taper angle which is controlled to be within predetermined range.Type: ApplicationFiled: November 30, 2004Publication date: July 21, 2005Applicant: NEC CorporationInventors: Nobuya Seko, Hitoshi Shiraishi, Kenichi Hayashi, Naoto Hirano, Atsushi Yamamoto
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Publication number: 20040219721Abstract: A semiconductor film serving as an active region of a thin film transistor and an upper oxide film protecting the semiconductor film are dry etched to form the active region. In this case, a fluorine-based gas is used as the etching gas, and the etching gas is switched from the fluorine-based gas to a chlorine-based gas at a point of time when a lower oxide film as an underlying film of the semiconductor film is exposed. As the fluorine-based gas, a mixed gas of CF4 and O2 is used, and suitably, a gas ratio of CF4 and O2 in the mixture gas is set at 1:1, and the dry etching is performed therefor. By this etching, a side face of a two-layer structure of the semiconductor film and upper oxide film is optimally tapered, and a crack or a disconnection is prevented from being occurring in a film crossing over the two-layer structure.Type: ApplicationFiled: May 28, 2004Publication date: November 4, 2004Applicant: NEC CorporationInventors: Hitoshi Shiraishi, Kenichi Hayashi, Naoto Hirano, Atsushi Yamamoto
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Publication number: 20030228760Abstract: A semiconductor film serving as an active region of a thin film transistor and an upper oxide film protecting the semiconductor film are dry etched to form the active region. In this case, a fluorine-based gas is used as the etching gas, and the etching gas is switched from the fluorine-based gas to a chlorine-based gas at a point of time when a lower oxide film as an underlying film of the semiconductor film is exposed. As the fluorine-based gas, a mixed gas of CF4 and O2 is used, and suitably, a gas ratio of CF4 and O2 in the mixture gas is set at 1:1, and the dry etching is performed therefor. By this etching, a side face of a two-layer structure of the semiconductor film and upper oxide film is optimally tapered, and a crack or a disconnection is prevented from being occurring in a film crossing over the two-layer structure.Type: ApplicationFiled: May 29, 2003Publication date: December 11, 2003Applicant: NEC CorporationInventors: Hitoshi Shiraishi, Kenichi Hayashi, Naoto Hirano, Atsushi Yamamoto
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Patent number: 5584914Abstract: The membrane deaerator according to the present invention includes a plurality of membrane deaerator modules and a water sealed vacuum pump connected thereto. These modules are series-connected between a raw water supply line and a deaeration water supply line. A first vacuum pump is connected to a first deaerator module via a deaeration line, and a second vacuum pump is connected to a second deaerator module via the deaeration line. These vacuum pumps are each provided with a seal water supply line which is used to send the raw water introduced from the water supply line thereinto as seal water to each of the first and second vacuum pumps. A discharge line for the second vacuum pump is connected to the deaeration line for the first vacuum pump. In the membrane deaerator thus formed, the deaeration performance is improved greatly, and a deaeration with dissolved oxygen concentration of several PPB can be carried out.Type: GrantFiled: February 7, 1995Date of Patent: December 17, 1996Assignees: Miura Co., Ltd, Miura Institute of Research & Development Co., Ltd.Inventors: Yasutoshi Senoo, Hitoshi Shiraishi, Norio Yasu, Yasuhiro Kawakami, Yukinori Tobisaka, Yasuo Ochi, Yasuhito Mitsukami, Toshitaka Shigematsu, Kazuhiro Tachino, Yasuhiro Miyagama, Kenichiro Takematsu, Nobuaki Yanagihara
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Patent number: 4825813Abstract: A multi-pipe once-through boiler having at least one row of a plurality of circumferentially arranged pipes on which a plurality of fins are arranged in such a manner that the fins are in contact with the flow of the combustion gas in a substantially parallel maner. Elements are provided for increasing the heat transfer effect, such as slits in the fins, or an inclined arrangement of the fins, or pipes without fins at the region near to the inlet of the combustion gas passageway, are provided. Furthermore, a heat insulating member for decreasing operational noise as well as a cleaner device for blow-cleaning the combustion gas passageway are provided.Type: GrantFiled: October 23, 1987Date of Patent: May 2, 1989Assignee: Miura Co., Ltd.Inventors: Yuji Yoshinari, Hitoshi Shiraishi, Osamu Tanaka, Akiyoshi Kawahito, Toshihiro Kayahara, Satoru Takeda, Takashi Yamada, Akinori Kawakami