Abstract: An element model of a high voltage MOS transistor having a low concentration impurity region between a channel region thereof and a drain electrode thereof is defined by combining a plurality of element models with each other. A basic characteristic is represented by a standard MOS model. A conductivity modulation effect of a low concentration drain diffusion layer is represented by a variable resistor model whose value is changed based upon both a drain voltage and a gate voltage. An overlap capacitance between a gate region and a drain region is represented by a MOS capacitance between the gate region and a bulk. A variable resistor model compensates that a voltage of channel edge portions located adjacent to the low concentration drain diffusion layer is changed by being influenced by not only the gate voltage, but also the drain voltage.

Abstract: A mixed mode simulation method and apparatus are provided for highly accurately simulating the total characteristics of a digital analyzed circuit portion and an analog analyzed circuit portion, which are both subjected to mixed mode simulation, in consideration of the influence exerted on the analog analyzed circuit portion by a current consumed by the digital analyzed circuit portion. More particularly, a current value of an equivalent circuit for current calculation modeled for providing the analog analyzed circuit portion with a current generated due to an operating state of the digital analyzed circuit portion realized by logic simulation is determined in synchronism with the logic simulation, and the equivalent circuit for current calculation derived thereby is composed with the analog analyzed circuit portion, and this composite circuit is subjected to circuit simulation.