Abstract: An information processing apparatus has a multi-valued NAND nonvolatile memory including a plurality of word lines and a plurality of memory cells connected to the respective word lines. Each memory cell has a plurality of threshold voltages, and is divided into a first and a second storage area. A program code is stored in the first storage area, and user data is stored in the second storage area. The apparatus also includes a volatile memory to which the program code is transferred from the multi-valued NAND nonvolatile memory. The apparatus further includes a CPU connected to the volatile memory and configured to operate based on the program code transferred to the volatile memory.

Abstract: An information processing apparatus has a multi-valued NAND nonvolatile memory including a plurality of word lines and a plurality of memory cells connected to the respective word lines. Each memory cell has a plurality of threshold voltages, and is divided into a first and a second storage area. A program code is stored in the first storage area, and user data is stored in the second storage area. The apparatus also includes a volatile memory to which the program code is transferred from the multi-valued NAND nonvolatile memory. The apparatus further includes a CPU connected to the volatile memory and configured to operate based on the program code transferred to the volatile memory.

Abstract: An information processing apparatus has a multi-valued NAND nonvolatile memory including a plurality of word lines and a plurality of memory cells connected to the respective word lines. Each memory cell has a plurality of threshold voltages, and is divided into a first and a second storage area. A program code is stored in the first storage area, and user data is stored in the second storage area. The apparatus also includes a volatile memory to which the program code is transferred from the multi-valued NAND nonvolatile memory. The apparatus further includes a CPU connected to the volatile memory and configured to operate based on the program code transferred to the volatile memory.

Abstract: A memory system including a nonvolatile semiconductor memory device and a controller. The memory device includes a plurality of word lines; and a plurality of memory cells each connected to a corresponding one of the word lines and each having N threshold voltages for storing multi-valued level, where N is a natural number of 4 or greater; wherein stored data in each of the plurality of memory cells constitutes a plurality of pages, at least only a part of multi-value level is used for storing data, a data “1” is always written to a lower page, a “0” or “1” binary data is written to an upper page, the same data is written in each of the pages when writing in the nonvolatile memory device, and only part of the pages to which the same data is written is accessed when reading out the nonvolatile memory device.

Abstract: An ECC control apparatus is to be connected between a host and a memory. The apparatus comprises a first input/output circuit, a detecting circuit, a code-generating circuit, a code-inserting circuit, a second input/output circuit. The first input/output circuit inputs and outputs data to and from the host. The detecting circuit detects a protected-data region and a redundant region of write data input to the first input/output circuit and having a predetermined data length. The code-generating circuit generates an error-correction code for correcting errors in data stored in the protected-data region. The code-inserting circuit inserts the error-correction code in the redundant region. The second input/output circuit inputs and outputs data to and from the memory.

Abstract: A processor boot-up controller includes: a volatile memory connected to a nonvolatile memory; a selector, which transfers boot-up codes to the volatile memory from the nonvolatile memory; a controller for the nonvolatile memory configured from a boot-up control sequencer, which transmits CPU read-in data to the CPU and brings the CPU into a wait state until boot-up code transfer completes; and an error detection and correction unit connected to the external CPU and the nonvolatile memory. The processor boot-up controls the CPU by reading data from the nonvolatile memory. The processor enables the CPU to access a SRAM in the shortest time in sync with the SRAM's ready timing, resulting in a reduction of average system boot-up time. An information processing system can use the controller for example for a nonvolatile memory, a microprocessor boot-up controller, and multi-valued nonvolatile memory.

Abstract: The present invention provides an SOI wafer having at least an SOI layer, in which a plain orientation of the SOI layer is off-angled from {110} only in a direction to <100>, and an off-angle is from 5 minutes to 2 degrees, and a method of producing an SOI wafer comprising at least bonding a base wafer and a bond wafer consisting of a silicon single crystal, and forming an SOI layer by thinning the bond wafer, wherein the bond wafer is used where a plain orientation thereof is off-angled from {110} only in a direction to <100>, and an off-angle is from 5 minutes to 2 degrees. Thereby, there can be provided an SOI wafer having both high uniformity of film thickness and good micro-roughness to be suitable for fabricating high speed devices, and provided a method of producing the SOI wafer.

Abstract: An information processing apparatus has a multi-valued NAND nonvolatile memory including a plurality of word lines and a plurality of memory cells connected to the respective word lines. Each memory cell has a plurality of threshold voltages, and is divided into a first and a second storage area. A program code is stored in the first storage area, and user data is stored in the second storage area. The apparatus also includes a volatile memory to which the program code is transferred from the multi-valued NAND nonvolatile memory. The apparatus further includes a CPU connected to the volatile memory and configured to operate based on the program code transferred to the volatile memory.

Abstract: A nonvolatile semiconductor memory controller has a plurality of word lines and a plurality of memory cells. Each memory cell is connected to a corresponding one of the word lines, and each memory cell has N threshold voltages, where N is a natural number of 4 or greater. The plurality of memory cells constitutes a plurality of pages, the same data is written in each of the pages when writing in the nonvolatile memory, and only part of the pages to which the same data is written is accessed when reading out the nonvolatile memory.

Abstract: A silicon epitaxial wafer (W) comprising: a silicon single crystal substrate (1) having a COP (100) on a main surface (11), and a silicon epitaxial layer (2) grown by vapor phase epitaxy on the main surface (11) of the silicon single crystal substrate (1), wherein the main surface (11) is inclined from a (100) plane in a [011] direction or a [0-1-1] direction by an angle ? with respect to a [100] axis as well as inclined from a (100) plane in a [01-1] direction or a [0-11] direction by an angle ? with respect to a [100] axis, and at least one of the angle ? and the angle ? is from 0° to 15?.

Abstract: The present invention provides an SOI wafer having at least an SOI layer, in which a plain orientation of the SOI layer is off-angled from {110} only in a direction to <100>, and an off-angle is from 5 minutes to 2 degrees, and a method of producing an SOI wafer comprising at least bonding a base wafer and a bond wafer consisting of a silicon single crystal, and forming an SOI layer by thinning the bond wafer, wherein the bond wafer is used where a plain orientation thereof is off-angled from {110} only in a direction to <100>, and an off-angle is from 5 minutes to 2 degrees. Thereby, there can be provided an SOI wafer having both high uniformity of film thickness and good micro-roughness to be suitable for fabricating high speed devices, and provided a method of producing the SOI wafer.

Abstract: The present invention enables a CPU to access a SRAM in the shortest time in sync with the SRAM's ready timing, resulting in a reduction of avarage system boot-up time. The present invention is a processor boot-up controller that includes: volatile memory, which is connected to nonvolatile memory; a selector, which transfers boot-up codes to the volatile memory from the nonvolatile memory; a controller for the nonvolatile memory which is configured from a boot-up control sequencer, which transmits CPU read-in data to the CPU and brings the CPU into a wait state until boot-up code transfer completes; and an error detection and correction unit; is connected to the external CPU and the nonvolatile memory, and boot-up controls the CPU by reading data from the nonvolatile memory. The present invention is an information processing system using a controller for nonvolatile memory, a microprocessor boot-up controller, and multi-valued nonvolatile memory.

Abstract: An ECC control apparatus is to be connected between a host and a memory. The apparatus comprises a first input/output circuit, a detecting circuit, a code-generating circuit, a code-inserting circuit, a second input/output circuit. The first input/output circuit inputs and outputs data to and from the host. The detecting circuit detects a protected-data region and a redundant region of write data input to the first input/output circuit and having a predetermined data length. The code-generating circuit generates an error-correction code for correcting errors in data stored in the protected-data region. The code-inserting circuit inserts the error-correction code in the redundant region. The second input/output circuit inputs and outputs data to and from the memory.

Abstract: There are disclosed a semiconductor wafer which has undulation components on wafer back surface and/or wafer front surface of 10 &mgr;m3 or less represented in terms of power spectrum density at least for the components at a wavelength of 10 mm; method for producing a semiconductor wafer by polishing front surface of the semiconductor wafer which is held at its back surface, which utilizes a semiconductor wafer to be polished having undulation components on wafer back surface of 10 &mgr;m3 or less represented in terms of power spectrum density at least for the components at a wavelength of 10 mm; and wafer chuck provided with a holding surface for holding a wafer by chucking, wherein the holding surface has undulation components of 10 &mgr;m3 or less represented in terms of power spectrum density at least for the components at a wavelength of 10 mm.

Abstract: There are disclosed a semiconductor wafer which has undulation components on wafer back surface and/or wafer front surface of 10 &mgr;m3 or less represented in terms of power spectrum density at least for the components at a wavelength of 10 mm; method for producing a semiconductor wafer by polishing front surface of the semiconductor wafer which is held at its back surface, which utilizes a semiconductor wafer to be polished having undulation components on wafer back surface of 10 &mgr;m3 or less represented in terms of power spectrum density at least for the components at a wavelength of 10 mm; and wafer chuck provided with a holding surface for holding a wafer by chucking, wherein the holding surface has undulation components of 10 &mgr;m3 or less represented in terms of power spectrum density at least for the components at a wavelength of 10 mm.

Abstract: The invention is predicated in an experimental finding that by setting the temperature in a wafer case, which is made of polypropyrene or like organic resin and in which wafers are stored, to -50.degree. to 15.degree. C., preferably to -50.degree. to 10.degree. C., it is possible to make the increase of organic materials attached during the storage of the wafers substantially to zero. The invention also concerns a method of determining the amount of organic materials attached to wafers, which comprises the steps of allowing a predetermined amount of water drop to be formed on the surface of a wafer, then measuring the angle .alpha. between the wafer and a line drawn from the contact point of 3 phases consisting of the water drop 10, the wafer 1 and gas on the wafer surface to the top of the water drop 10, and thereby obtaining the contact angle .theta. as .theta.=2.alpha., and then determining the amount of organic materials from the contact angle .theta..

Abstract: A method for vapor-phase growth which allows an epiwafer of a smooth surface free from microroughness to be produced is provided. This method comprises a step of heating up a silicon single crystal substrate in an ambience of an inert gas started at a temperature of less than 800.degree. C. and a step of removing a native oxide film formed on the surface of the silicon single crystal substrate by etching with hydrogen gas in an ambience of hydrogen gas at a temperature of not less than 950.degree. C. and not more than 1190.degree. C. prior to the vapor-phase growth.