Patents by Inventor Hitoshi Ueno

Hitoshi Ueno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12627898
    Abstract: A load management system includes: an image acquisition sensor configured to acquire image data including an analysis target image including a load loaded in a medium processing apparatus; a judgment circuitry configured to judge whether or not the image data is authentic; and an image analysis circuitry configured to analyze the analysis target image to acquire information about the load when the image data is authentic.
    Type: Grant
    Filed: February 13, 2023
    Date of Patent: May 12, 2026
    Assignee: GLORY LTD.
    Inventor: Hitoshi Ueno
  • Patent number: 12609007
    Abstract: A medium processing system includes: a memory and a processor, in which the processor performs application execution for exchanging transaction information with a device via middleware to perform information processing on a transaction of a valuable medium, the device being configured to perform the transaction, and error processing of acquiring, upon occurrence of an error in the device during the transaction of the valuable medium, first error information from among pieces of information on the error without the middleware to perform error recovery processing on the error based on the first error information.
    Type: Grant
    Filed: March 13, 2024
    Date of Patent: April 21, 2026
    Assignee: GLORY, LTD.
    Inventors: Takuma Oda, Hitoshi Ueno
  • Patent number: 12438292
    Abstract: An electronic device includes a substrate having a first surface and a second surface in a front-back relation, a first electronic component mounted on the second surface, and a lead joined to the second surface of the substrate via a conductive joint member, wherein the lead includes a base end portion extending in a direction along the substrate and joined to the second surface via the joint member, a distal end portion located distally from the substrate with respect to the base end portion in a thickness direction of the substrate and having a terminal surface, and a coupling portion coupling the base end portion and the distal end portion, and ?1>?2, wherein, as seen from a direction orthogonal to a plane along which the lead extends, an angle formed by a line connecting an outermost position in which the joint member contacts the base end portion and an outer edge of the substrate and the base end portion is ?1, a distance between the first electronic component and the terminal surface in the thickne
    Type: Grant
    Filed: November 10, 2023
    Date of Patent: October 7, 2025
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Hitoshi Ueno
  • Publication number: 20250155466
    Abstract: In a method for manufacturing an electronic device, a first electronic device includes a first sensor, a second sensor, a first circuit board, and a first package, a second electronic device includes a third sensor, a fourth sensor, a second circuit board, and a second package, the first package and the second package have the same size in plan view, the second sensor has a size smaller than a size of the fourth sensor in plan view, the first circuit board and the second circuit board have the same size in plan view, and the method includes: mounting the first circuit board on the first package and then mounting the second sensor; and mounting the fourth sensor on the second package and then mounting the second circuit board.
    Type: Application
    Filed: November 13, 2024
    Publication date: May 15, 2025
    Inventor: Hitoshi UENO
  • Publication number: 20240311229
    Abstract: A medium processing system includes: a memory and a processor, in which the processor performs application execution for exchanging transaction information with a device via middleware to perform information processing on a transaction of a valuable medium, the device being configured to perform the transaction, and error processing of acquiring, upon occurrence of an error in the device during the transaction of the valuable medium, first error information from among pieces of information 10 on the error without the middleware to perform error recovery processing on the error based on the first error information.
    Type: Application
    Filed: March 13, 2024
    Publication date: September 19, 2024
    Inventors: Takuma ODA, Hitoshi UENO
  • Publication number: 20240162637
    Abstract: An electronic device includes a substrate having a first surface and a second surface in a front-back relation, a first electronic component mounted on the second surface, and a lead joined to the second surface of the substrate via a conductive joint member, wherein the lead includes a base end portion extending in a direction along the substrate and joined to the second surface via the joint member, a distal end portion located distally from the substrate with respect to the base end portion in a thickness direction of the substrate and having a terminal surface, and a coupling portion coupling the base end portion and the distal end portion, and ?1>?2, wherein, as seen from a direction orthogonal to a plane along which the lead extends, an angle formed by a line connecting an outermost position in which the joint member contacts the base end portion and an outer edge of the substrate and the base end portion is ?1, a distance between the first electronic component and the terminal surface in the thickne
    Type: Application
    Filed: November 10, 2023
    Publication date: May 16, 2024
    Inventor: Hitoshi UENO
  • Patent number: 11776860
    Abstract: A method of manufacturing an electronic device includes a preparation step of preparing a substrate to which a lead is bonded, and a molding step of mounting a cap in a mold in a state in which the cap is disposed on the substrate and forming a mold portion by filling a mold material into the mold. The mold includes a first mold including a cap mounting portion, and a second mold including a lead pressing portion. The molding step includes a step of mounting the cap in the cap mounting portion, a step of mounting the substrate on the cap, a step of pressing the lead with the lead pressing portion to elastically deform the lead, and biasing the substrate toward the cap by a restoring force generated in the lead, and a step of filling the mold material into the mold.
    Type: Grant
    Filed: September 10, 2021
    Date of Patent: October 3, 2023
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Masataka Kazuno, Tetsuya Otsuki, Hitoshi Ueno
  • Publication number: 20230276138
    Abstract: A load management system includes: an image acquisition sensor configured to acquire image data including an analysis target image including a load loaded in a medium processing apparatus; a judgment circuitry configured to judge whether or not the image data is authentic; and an image analysis circuitry configured to analyze the analysis target image to acquire information about the load when the image data is authentic.
    Type: Application
    Filed: February 13, 2023
    Publication date: August 31, 2023
    Inventor: Hitoshi Ueno
  • Publication number: 20230209716
    Abstract: A sensor module includes a circuit board, a sensor element having a detection axis along a planar direction of the circuit board, a sensor package accommodating the sensor element and mounted on the circuit board, a board land pattern used for mounting the sensor package disposed on the circuit board, and a package electrode disposed on a mounting surface of the sensor package facing the circuit board and joined to the board land pattern by a solder. A relationship of Xp?X1 is satisfied, in which Xp is a width of the board land pattern in a first direction along the planar direction of the circuit board, and X1 is a width of the package electrode in the first direction.
    Type: Application
    Filed: December 22, 2022
    Publication date: June 29, 2023
    Inventor: Hitoshi UENO
  • Patent number: 11688727
    Abstract: An electronic device includes: a substrate; a first electronic component that is mounted on a first surface of the substrate; a cap that accommodates the first electronic component between the cap and the substrate; and a mold portion that bonds the cap and the substrate. The cap includes a base portion having a recess that opens to a substrate side and accommodates the first electronic component, and a flange portion that protrudes from an end portion of the base portion on the substrate side to an outer peripheral side and is in contact with the first surface. The mold portion is provided from a second surface side of the substrate to a first surface side while bypassing a side, and bonds the cap and the substrate by molding the flange portion in a portion on the first surface side.
    Type: Grant
    Filed: September 10, 2021
    Date of Patent: June 27, 2023
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Masataka Kazuno, Tetsuya Otsuki, Hitoshi Ueno
  • Patent number: 11659664
    Abstract: An electronic device includes: a substrate having an upper surface and a lower surface; a first electronic component mounted on the upper surface of the substrate; a second electronic component mounted on the lower surface of the substrate; and a mold portion covering the second electronic component without covering the first electronic component. The first electronic component is bonded to the upper surface on the first relative surface via a conductive first bonding member. The second electronic component is bonded to the lower surface via a second bonding member on a second relative surface relative to the lower surface.
    Type: Grant
    Filed: September 10, 2021
    Date of Patent: May 23, 2023
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Masataka Kazuno, Tetsuya Otsuki, Hitoshi Ueno
  • Patent number: 11595284
    Abstract: The process includes acquiring, from a relay device that relays a packet between a first communication device and a second communication device, a plurality of first delay times generated by a round trip of the packet between the first communication device and the relay device, and a plurality of second delay times generated by a round trip of the packet between the second communication device and the relay device, sorting separately the plurality of first delay times and the plurality of second delay times based on a length of a delay time, and calculating device delay times based on a first delay calculation that calculates a difference between each of the plurality of first delay times and each of the plurality of second delay times in a same rank after the sorting.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: February 28, 2023
    Assignee: FUJITSU LIMITED
    Inventors: Sumiyo Okada, Hitoshi Ueno, Fumiyuki Iizuka, Kazutaka Ogihara, Chunghan Lee
  • Patent number: 11507076
    Abstract: A computer readable network analysis program of performing local modeling analysis of determining an estimated value of a current network quality corresponding to explanatory variable vector in current aggregated data based on a local model including local training data; determining an abnormality in the network based on whether or not a measured value of the current network quality is lower than a threshold; determining whether or not a distribution of the connections having the measured value of the network quality exceeding the threshold is present in a large size; extracting an individual-analysis-target connection group including more than predetermined proportions of connections in the distribution of the connections having the large size; and performing the local modeling analysis to the individual-analysis-target connection group and the remaining connection groups to determine the abnormality in the network.
    Type: Grant
    Filed: June 10, 2020
    Date of Patent: November 22, 2022
    Assignee: FUJITSU LIMITED
    Inventors: Fumiyuki Iizuka, Hitoshi Ueno
  • Publication number: 20220253364
    Abstract: A method of calculating a predicted exhaustion date for causing a computer to execute a process. The process includes calculating a first predicted exhaustion date when a resource in a system is predicted to be exhausted, at a first time point, calculating: a second predicted exhaustion date when the resource is predicted to be exhausted, at a second time point after the first time point, calculating a difference between the first predicted exhaustion date and the second predicted exhaustion date, calculating, a third predicted exhaustion date by con-ecting the second predicted exhaustion date based on the difference, and presenting the third predicted exhaustion date.
    Type: Application
    Filed: October 5, 2021
    Publication date: August 11, 2022
    Applicant: FUJITSU LIMITED
    Inventors: Tatsuo Kumano, Hitoshi UENO
  • Publication number: 20220237099
    Abstract: A service specifying method for causing a computer to execute a process. The process includes acquiring a parameter indicating a load of a resource used by a plurality of services for each of the plurality of services, estimating a performance of each service for each of a plurality of the services by using an estimation model that estimates the performance of the each service from the parameter related to the each service, the estimation model being provided for each of the plurality of services, and specifying, among the plurality of services, a service whose performance is deteriorated due to a failure of the resource based on the estimated performance.
    Type: Application
    Filed: October 4, 2021
    Publication date: July 28, 2022
    Applicant: FUJITSU LIMITED
    Inventors: Takashi Shiraishi, Reiko Kondo, Hitoshi UENO
  • Publication number: 20220084898
    Abstract: A method of manufacturing an electronic device includes a preparation step of preparing a substrate to which a lead is bonded, and a molding step of mounting a cap in a mold in a state in which the cap is disposed on the substrate and forming a mold portion by filling a mold material into the mold. The mold includes a first mold including a cap mounting portion, and a second mold including a lead pressing portion. The molding step includes a step of mounting the cap in the cap mounting portion, a step of mounting the substrate on the cap, a step of pressing the lead with the lead pressing portion to elastically deform the lead, and biasing the substrate toward the cap by a restoring force generated in the lead, and a step of filling the mold material into the mold.
    Type: Application
    Filed: September 10, 2021
    Publication date: March 17, 2022
    Inventors: Masataka Kazuno, Tetsuya Otsuki, Hitoshi Ueno
  • Publication number: 20220085004
    Abstract: An electronic device includes: a substrate; a first electronic component that is mounted on a first surface of the substrate; a cap that accommodates the first electronic component between the cap and the substrate; and a mold portion that bonds the cap and the substrate. The cap includes a base portion having a recess that opens to a substrate side and accommodates the first electronic component, and a flange portion that protrudes from an end portion of the base portion on the substrate side to an outer peripheral side and is in contact with the first surface. The mold portion is provided from a second surface side of the substrate to a first surface side while bypassing a side, and bonds the cap and the substrate by molding the flange portion in a portion on the first surface side.
    Type: Application
    Filed: September 10, 2021
    Publication date: March 17, 2022
    Inventors: Masataka Kazuno, Tetsuya Otsuki, Hitoshi Ueno
  • Publication number: 20220087023
    Abstract: An electronic device includes: a substrate having an upper surface and a lower surface; a first electronic component mounted on the upper surface of the substrate; a second electronic component mounted on the lower surface of the substrate; and a mold portion covering the second electronic component without covering the first electronic component. The first electronic component is bonded to the upper surface on the first relative surface via a conductive first bonding member. The second electronic component is bonded to the lower surface via a second bonding member on a second relative surface relative to the lower surface.
    Type: Application
    Filed: September 10, 2021
    Publication date: March 17, 2022
    Inventors: Masataka Kazuno, Tetsuya Otsuki, Hitoshi Ueno
  • Patent number: 11233886
    Abstract: A non-transitory computer-readable storage medium storing a packet analysis program for causing a computer to execute a process, the process includes acquiring packets communicated between nodes, adding information of communication of ongoing couplings to an ongoing coupling list in each of predetermined time ranges belonging to start times of the couplings based on the packets, and removing information of communication of a terminated coupling from the ongoing coupling list based on the packets, and analyzing the quality of the communication of the terminated coupling in a cycle corresponding to a time range among the time ranges, and analyzing the quality of communication related to a coupling present in the ongoing coupling list even when the cycle has elapsed a predetermined number of times or more after the addition of information of the coupling to the ongoing coupling list.
    Type: Grant
    Filed: April 8, 2020
    Date of Patent: January 25, 2022
    Assignee: FUJITSU LIMITED
    Inventors: Fumiyuki Iizuka, Hitoshi Ueno
  • Patent number: 11055146
    Abstract: A distribution process system includes a first terminal configured to, in accordance with a change relating to a processing load, perform transmission of first information relating to the processing load of the first terminal to a second terminal having a transmission frequency of a message relating to a processing load of the second terminal to a management device higher than a transmission frequency of a message relating to the processing load of the first terminal, the second terminal configured to, in response to receiving the first information, transmit to the management device a first message relating to the processing load of the second terminal and the first information, and the management device configured to manage a load state of each of the first terminal and the second terminal, and update the load state of the first terminal in accordance with the first information in response to receiving the first information.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: July 6, 2021
    Assignee: FUJITSU LIMITED
    Inventors: Takashi Enami, Masanori Yamazaki, Nami Nagata, Hitoshi Ueno