Patents by Inventor Hitoshi Yamanaka
Hitoshi Yamanaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11673214Abstract: A lead-free solder contains 93.0 mass % or more and 98.95 mass % or less of indium, 1.0 mass % or more and 4.0 mass % or less of tin, and an addition metal. The addition metal contains at least one of silver, antimony, copper, or nickel. The addition metal is neither indium nor tin. The total of mass percentage of the addition metal is 0.05 mass % or more and 6.0 mass % or less. The sum of the total mass percentage of the addition metal, the mass percentage of indium, and the mass percentage of tin is 100 mass % or less.Type: GrantFiled: May 25, 2022Date of Patent: June 13, 2023Assignee: Uchihashi Estec Co., Ltd.Inventors: Yoshihiro Yoshioka, Kazuo Inada, Tomokuni Mitsui, Hitoshi Yamanaka
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Publication number: 20220379411Abstract: A lead-free solder contains 93.0 mass % or more and 98.95 mass % or less of indium, 1.0 mass % or more and 4.0 mass % or less of tin, and an addition metal. The addition metal contains at least one of silver, antimony, copper, or nickel. The addition metal is neither indium nor tin. The total of mass percentage of the addition metal is 0.05 mass % or more and 6.0 mass % or less. The sum of the total mass percentage of the addition metal, the mass percentage of indium, and the mass percentage of tin is 100 mass % or less.Type: ApplicationFiled: May 25, 2022Publication date: December 1, 2022Applicant: Uchihashi Estec Co., Ltd.Inventors: Yoshihiro YOSHIOKA, Kazuo INADA, Tomokuni MITSUI, Hitoshi YAMANAKA
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Publication number: 20140068193Abstract: An address range of an L2 cache is divided into sets of a predetermined number of ways. A RAM-BIST pattern generating unit generates a memory address corresponding to a way, a test pattern, and an expected value with respect to the test pattern. The L2 cache and an XOR circuit write the test pattern to a memory address in accordance with the test pattern, read data from the memory address to which the test pattern is written, and compares the read data with the expected value. A decode unit generates a selection signal for each way of the L2 cache by using a memory address. A determination latch stores, by using a selection signal and in a way corresponding to each memory address, a comparison result with respect to the memory address, a scan-out being performed on the comparison result stored in each of the ways in a predetermined order.Type: ApplicationFiled: July 24, 2013Publication date: March 6, 2014Applicants: FUJITSU SEMICONDUCTOR LIMITED, FUJITSU LIMITEDInventors: Hitoshi YAMANAKA, Kenichi GOMI
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Patent number: 8356217Abstract: A storage circuit, an integrated circuit and a scanning method are provided. The storage circuit includes a first storage element, and a second storage element connected to an output of the first storage element. The storage circuit includes a first setting circuit that is configured to set data of a first logic value to the first storage element when a clear signal is applied, and a second setting circuit that is configured to set data of a second logic value to the second storage element and transmit the second logic value data to a different storage circuit when a second clock signal is in an off state and the clear signal is applied.Type: GrantFiled: May 25, 2010Date of Patent: January 15, 2013Assignee: Fujitsu LimitedInventors: Hitoshi Yamanaka, Masahiro Yanagida
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Publication number: 20100332930Abstract: A storage circuit, an integrated circuit and a scanning method are provided. The storage circuit includes a first storage element, and a second storage element connected to an output of the first storage element. The storage circuit includes a first setting circuit that is configured to set data of a first logic value to the first storage element when a clear signal is applied, and a second setting circuit that is configured to set data of a second logic value to the second storage element and transmit the second logic value data to a different storage circuit when a second clock signal is in an off state and the clear signal is applied.Type: ApplicationFiled: May 25, 2010Publication date: December 30, 2010Applicant: FUJITSU LIMITEDInventors: Hitoshi YAMANAKA, Masahiro YANAGIDA
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Patent number: 7734973Abstract: An apparatus enables a high quality test to be carried out within a short time, without forcing a severe design limitation on the designer and without an expensive tester. The apparatus includes a pattern generator built in an integrated circuit to generate pseudo random patterns as test patterns. A plurality of shift registers are configured with sequential circuit elements inside said integrated circuit. An automatic test pattern generating unit generates ATPG patterns. A pattern modifier modifies a portion, to which a predetermined value is required to be set in order to detect a fault, in said pseudo random patterns generated by said pattern generator, on a basis of said ATPG patterns, and inputs said modified pseudo random patterns to said shift registers.Type: GrantFiled: December 29, 2006Date of Patent: June 8, 2010Assignee: Fujitsu Microelectronics LimitedInventors: Takahisa Hiraide, Hitoshi Yamanaka
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Patent number: 7353440Abstract: In processors having multiple cores, such as CMPs, an independent MISR test pattern compression circuit is provided for each logic block, which makes it possible to perform LSI tests more efficiently. A processor includes a plurality of logic block circuits, which include at least a first processor core circuit and a second processor core circuit, each processor core circuit having a scan chain circuit and being operable independently, and a common block circuit having a scan chain circuit and a cache circuit that is shared by the first processor core circuits and the second processor core circuits. The processor further includes, for each logic block, a test pattern generating circuit operable to generate a test pattern and input the test pattern to the scan chain of each logic block circuit, and a test pattern compression circuit operable to accept as input and compress the test pattern output by the scan chain of each logic block circuit.Type: GrantFiled: October 19, 2004Date of Patent: April 1, 2008Assignee: Fujitsu LimitedInventors: Akihiko Ohwada, Tatsumi Nakada, Hitoshi Yamanaka
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Publication number: 20070168816Abstract: An apparatus enables a high quality test to be carried out within a short time, without forcing a severe design limitation on the designer and without an expensive tester. The apparatus includes a pattern generator built in an integrated circuit to generate pseudo random patterns as test patterns. A plurality of shift registers are configured with sequential circuit elements inside said integrated circuit. An automatic test pattern generating unit generates ATPG patterns. A pattern modifier modifies a portion, to which a predetermined value is required to be set in order to detect a fault, in said pseudo random patterns generated by said pattern generator, on a basis of said ATPG patterns, and inputs said modified pseudo random patterns to said shift registers.Type: ApplicationFiled: December 29, 2006Publication date: July 19, 2007Applicant: FUJITSU LIMITEDInventors: Takahisa Hiraide, Hitoshi Yamanaka, Junko Kumagai, Hideaki Konishi, Daisuke Maruyama
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Patent number: 7178078Abstract: An apparatus enables a high quality test to be carried out within a short time, without forcing a severe design limitation on the designer and without an expensive tester. The apparatus includes a pattern generator built in an integrated circuit to generate pseudo random patterns as test patterns. A plurality of shift registers are configured with sequential circuit elements inside said integrated circuit. An automatic test pattern generating unit generates ATPG patterns. A pattern modifier modifies a portion, to which a predetermined value is required to be set in order to detect a fault, in said pseudo random patterns generated by said pattern generator, on a basis of said ATPG patterns, and inputs said modified pseudo random patterns to said shift registers.Type: GrantFiled: December 4, 2001Date of Patent: February 13, 2007Assignee: Fujitsu LimitedInventors: Takahisa Hiraide, Hitoshi Yamanaka, Junko Kumagai, Hideaki Konishi, Daisuke Maruyama
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Publication number: 20050240850Abstract: In processors having a multicore, such as CMPs, an independent MISR test pattern compression circuit is provided for each logic block in a multicore processor such as a CMP comprising a plurality of processor cores makes it possible to perform LSI tests more efficiently.Type: ApplicationFiled: October 19, 2004Publication date: October 27, 2005Inventors: Akihiko Ohwada, Tatsumi Nakada, Hitoshi Yamanaka
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Publication number: 20020124217Abstract: An apparatus enables a high quality test to be carried out within a short time, without forcing a severe design limitation on the designer and without an expensive tester. The apparatus comprises a pattern generator built in an integrated circuit to generate a test pattern, a plurality of shift registers configured with sequential circuit elements F/Fs inside the integrated circuit, and a pattern modifier modifying the test pattern generated by the pattern generator according to an external input, and inputting it to the plural shift registers. The apparatus is used as a testing apparatus for detecting manufacturing failure of an integrated circuit such as an LSI (Large Scale Integration) or the like.Type: ApplicationFiled: December 4, 2001Publication date: September 5, 2002Applicant: FUJITSU LIMITEDInventors: Takahisa Hiraide, Hitoshi Yamanaka, Junko Kumagai, Hideaki Konishi, Daisuke Maruyama