Patents by Inventor Hitoshi Yanami

Hitoshi Yanami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090182539
    Abstract: An objective function can be mathematically approximated using a prescribed number of sample sets of design parameters and sets of a plurality of objective functions computed corresponding to them. A logical expression indicating a relation between or among arbitrary two or three objective functions of the plurality of mathematically approximated objective functions is computed as an inter-objective-function logical expression and a region that the arbitrary objective function values can take is displayed as a feasible region in an objective space corresponding to the arbitrary objective functions. Furthermore, a point or area in a design space corresponding to arbitrary design parameters corresponding to a point or area specified by a user in the displayed feasible region is displayed.
    Type: Application
    Filed: December 31, 2008
    Publication date: July 16, 2009
    Applicant: FUJITSU LIMITED
    Inventors: Hirokazu Anai, Hitoshi Yanami, Tsuneo Nakata
  • Publication number: 20090182695
    Abstract: A logical expression indicating a logical relation between arbitrary two or three objective functions, of a plurality of mathematically approximated objective functions is computed. A feasible region/sensitivity information display unit displays the feasible region in arbitrary objective space according to it. An inverse image computation unit computes a point or area in design space corresponding to arbitrary design parameters in relation to a point or area specified by a user in the feasible region of the objective space. A feasible region/sensitivity information display unit displays the distribution state of the corresponding point or area as sensitivity information in relation to the specified point or area in the feasible region.
    Type: Application
    Filed: December 31, 2008
    Publication date: July 16, 2009
    Applicant: FUJITSU LIMITED
    Inventors: Hitoshi Yanami, Hirokazu Anai, Naozumi Tsuda
  • Publication number: 20090182538
    Abstract: A unit 101 calculates a plurality of sets of objective functions of sample sets of input parameters. A unit 102 approximates the objective functions using a polynomial on the basis of the calculation result of the unit 101. A unit 103 calculates a logical expression indicating a logical relation between arbitrary two or three objective functions, of the plurality of mathematically approximated objective functions as an inter-objective function logical expression by a QE method. A unit 104 displays areas that the values of the objective functions can take as usable areas according to the inter-objective function logical expression. Units 105 and 106 determine an optimum set of design parameters by limiting the sets of design parameters to corresponding sets of design parameters in the neighborhood of a Pareto boundary on the basis of the Pareto boundary of an objective function recognized from the usable areas displayed.
    Type: Application
    Filed: December 31, 2008
    Publication date: July 16, 2009
    Applicant: FUJITSU LIMITED
    Inventors: Hitoshi Yanami, Hirokazu Anai, Tsuneo Nakata, Naozumi Tsuda
  • Patent number: 6956951
    Abstract: Intermediate data ai, bi, ci, and di are prepared by an intermediate data preparing equipment 4 from a cryptographic key through a nonlinear type function operation and the like, an extended key preparing equipment 5 selects a [Xr], b [Yr], c [Zr], and d [Wr] corresponding to the number of stages r from the intermediate data, and rearranges the data as well as conducts that of bit operation to prepare extended keys, whereby an extended key preparing apparatus by which an extended key required in the case where common key cryptosystem is applied can be safely prepared at a high speed, a process for preparing such an extended key, and a recording medium used therefor are provided.
    Type: Grant
    Filed: March 20, 2001
    Date of Patent: October 18, 2005
    Assignee: Fujitsu Limited
    Inventors: Takeshi Shimoyama, Koichi Ito, Masahiko Takenaka, Naoya Torii, Jun Yajima, Hitoshi Yanami, Kazuhiro Yokoyama
  • Publication number: 20020021801
    Abstract: By providing a unit receiving the input of a set T of bit numbers that are obtained by unequally dividing all the bit numbers of input data to be given to a computing apparatus, a unit outputting a value AT indicating an existence probability of an appropriate linear converting unit corresponding to a plurality of S boxes of which the input and output bit numbers are equivalent to the divided bit numbers, a unit determining that an appropriate linear converting unit is present when the value of AT is positive, and a unit forming a pseudo MDS matrix as the linear converting unit, computation is executed using a unit with an excellent data diffusion performance as the linear converting unit in SPN structure, when the input number is not the same as the output number among a plurality of S boxes of the SPN structure in an F function.
    Type: Application
    Filed: March 21, 2001
    Publication date: February 21, 2002
    Inventors: Takeshi Shimoyama, Koichi Ito, Masahiko Takenaka, Naoya Torii, Jun Yajima, Hitoshi Yanami, Kazuhiro Yokoyama
  • Publication number: 20020006196
    Abstract: Intermediate data ai, bi, ci, and di are prepared by an intermediate data preparing equipment 4 from a cryptographic key through a nonlinear type function operation and the like, an extended key preparing equipment 5 selects a [Xr], b [Yr], c [Zr], and d [Wr] corresponding to the number of stages r from the intermediate data, and rearranges the data as well as conducts that of bit operation to prepare extended keys, whereby an extended key preparing apparatus by which an extended key required in the case where common key cryptosystem is applied can be safely prepared at a high speed, a process for preparing such an extended key, and a recording medium used therefor are provided.
    Type: Application
    Filed: March 20, 2001
    Publication date: January 17, 2002
    Inventors: Takeshi Shimoyama, Koichi Ito, Masahiko Takenaka, Naoya Torii, Jun Yajima, Hitoshi Yanami, Kazuhiro Yokoyama