Patents by Inventor Hitoshi Yokono
Hitoshi Yokono has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 5569545Abstract: A copper clad laminate having a bonded side ensuring powerful adhesion between the copper foil and insulating layer, without providing protrusions on the copper foil or making roughing treatment or black treatment, by designing such a configuration that the copper foil has a metal layer on the side to be bonded with the insulating layer and the metal layer and insulating layer are cross-linked with each other by chemical bonds through sulfur atoms. Further, there is provided a multilayer printed circuit board which has a bonded side ensuring a powerful adhesion of the circuit copper foil and insulating layer, by designing such a configuration that the alternating metal layers and insulating layers are cross-linked with each other by chemical bonds through sulfur atoms.Type: GrantFiled: December 28, 1994Date of Patent: October 29, 1996Assignee: Nippon Denkai Ltd.Inventors: Hitoshi Yokono, Haruki Yokono, Masahiro Mikamo, Ryouichi Narushima, Takuya Iida, Yasuhiro Endo
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Patent number: 5393406Abstract: A thin film multilayer wiring board-producing method of the present invention is intended to decrease thermal stresses developing during the formation of the multilayer construction, and also to greatly reduce the number of the steps of the process, as compared with a conventional method. A film material can be used as an insulating film of the multilayer wiring board, and is adhesively bonded to a predetermined portion. Wiring conductors are formed by electroplating. The wiring layers are repeated laminated to form the multilayer construction. A metallic film serving as an electrode is formed on one of upper and lower surfaces of a substrate, the metallic film being removed after a multilayer wiring is formed. A soluble insulating film is formed on a metallic undercoat film on the substrate, and grooves are formed in the soluble insulating film, and wiring conductors are formed in the grooves, using either electroplating or both electroplating and electroless plating.Type: GrantFiled: March 4, 1992Date of Patent: February 28, 1995Assignee: Hitachi, Ltd.Inventors: Hitoshi Yokono, Hideo Arima, Takashi Inoue, Naoya Kitamura
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Patent number: 5388328Abstract: A process for the fabrication of an interconnected multilayer board involves the steps of forming a metallic under-conductive layer on a base substrate, forming a windowed resist layer on the metallic under-conductive layer, filling windows of the resist layer with a conductor by plating thereby forming a conductor layer, forming another windowed resist layer on the conductor layer and filling windows of this resist layer with a conductor by plating, thereby forming a via-hole layer and to provide a two-level structure of the conductor layer and the via-hole layer. Thereafter, the resist layers and portions of the metallic under-conductor layer other than those in contact with a lower face of the conductor constituting the conductor layer are dissolved to form a two-level skeleton structure of conductor lines and spaces within the skeleton structure are filled with a varnish in a solventless form and the varnish is cured.Type: GrantFiled: January 28, 1994Date of Patent: February 14, 1995Assignee: Hitachi, Ltd.Inventors: Hitoshi Yokono, Hideo Arima, Takashi Inoue, Naoya Kitamura, Haruhiko Matsuyama, Hitoshi Oka, Fumio Kataoka, Fusaji Shoji, Hideyasu Murooka, Masayuki Kyooi
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Patent number: 5300735Abstract: Described herein are interconnected mutilayer boards and their fabrication processes. Multilayer conductor lines of a skeleton structure are formed by conducting multilayer metallization while including all resist layers and metallic under-conductive layers and then removing the resist layers and metallic under-conductive layers at once. Spaces between the multilayer conductor lines of the skeleton structure are then filled with a solventless varnish so that insulating layers are formed. Modules making use of such interconnected multilayer boards and computers having such modules are also described.Type: GrantFiled: March 22, 1993Date of Patent: April 5, 1994Assignee: Hitachi, Ltd.Inventors: Hitoshi Yokono, Hideo Arima, Takashi Inoue, Naoya Kitamura, Haruhiko Matsuyama, Hitoshi Oka, Fumio Kataoka, Fusaji Shoji, Hideyasu Murooka, Masayuki Kyooi
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Patent number: 5208656Abstract: A multilayer wiring substrate having high reliability can be produced in good productivity by subjecting metal wiring layers to stabilization treatment on the surface with a metal such as Cr, Mo or the like or an aqueous solution of water glass so as to prevent generation of hillocks or whiskers and to improve chemical resistance.Type: GrantFiled: March 25, 1991Date of Patent: May 4, 1993Assignee: Hitachi, Ltd.Inventors: Haruhiko Matsuyama, Mitsuo Yoshimoto, Jun Tanaka, Fusaji Shoji, Hitoshi Yokono, Takashi Inoue, Tetsuya Yamazaki, Minoru Tanaka, Hidetaka Shigi
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Patent number: 5202151Abstract: The present invention relates to an electroless gold plating solution, a method of plating by using the same, and an electronic device plated with gold by using the same.According to the present electroless gold plating solution, the plating solution components contain no cyanide ions, the amount of a reducing agent used is small, and gold plating can be carried out without causing the gold plating on conducting paths having a fine interval between them to short-circuit the conducting paths.Therefore, according to the method of gold plating by using said electroless gold plating solution, a plating method that is safe in the plating work and in the treatment of its waste liquor can be accomplished. The method has a feature that the method can provide an electronic device on which parts can be mounted highly densely, and wherein the joint reliability to the parts is high.Type: GrantFiled: June 4, 1990Date of Patent: April 13, 1993Assignee: Hitachi, Ltd.Inventors: Jiro Ushio, Osamu Miyazawa, Akira Tomizawa, Hitoshi Yokono, Naoya Kanda, Naoko Matsuura, Setsuo Ando, Hiroaki Okudaira
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Patent number: 5198273Abstract: The present invention provides an electroless gold plating solution comprising essentially gold ions, a complexing agent, and a reducing agent, characterized by further containing a reduction promoter which has a function of giving electrons to an oxidant, the oxidant being produced from oxidation of the reducing agent with the gold ions being reduced, to change the oxidant to the original reducing agent. The present invention also provides a process for conducting electroless gold plating by bringing a substrate into contact with the electroless gold plating solution. The plating solution is excellent in the stability for gold plating of high deposition rate. Thus the present invention allows the electroless gold plating to be performed stably at a higher deposition rate.Type: GrantFiled: September 11, 1990Date of Patent: March 30, 1993Assignees: Hitachi, Ltd., Hitachi Chemical Company, Ltd.Inventors: Setsuo Ando, Jiro Ushio, Takashi Inoue, Hiroaki Okudaira, Takeshi Shimazaki, Hitoshi Yokono
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Patent number: 5162240Abstract: A thick and thin film hybrid multilayer wiring substrate includes an adjustment layer provided between a thick film circuit and a thin film circuit in order to adjust positions of the thick film circuit and the thin film circuit with high integration and large area of the thick and thin film hybrid substrate. The adjustment layer is formed using a direct printing process in accordance with dispersion of the shape of the thick film circuit substrate to absorb the dispersion of the substrate. Further, in order to absorb dispersion of contraction of the thick film substrate due to sintering, a position of a mark provided on the substrate is detected by an electron beam and thereafter a connection pattern is formed to be connected to a regular pattern.Type: GrantFiled: June 12, 1990Date of Patent: November 10, 1992Assignee: Hitachi, Ltd.Inventors: Norio Saitou, Hideo Todokoro, Katsuhiro Kuroda, Satoru Fukuhara, Genya Matsuoka, Hideo Arima, Hitoshi Yokono, Takashi Inoue, Hidetaka Shigi
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Patent number: 5133403Abstract: A cooling device for cooling semiconductor elements by removing heat generated from the semiconductor elements such as, for example, semiconductor integrated chips in a large-sized electronic computer. The cooling device is fashioned of a composite AlN-BN sintered material having a Vickers hardness not higher than one-fifth of that of an AlN material, and an anisotropic property of thermal conductivity in a two dimensional direction is higher than that of AlN which is isotropic in thermal conductivity. The cooling device may be mass-produced while nevertheless having a high transfer performance matching the quantity of heat generated for each semiconductor element even if the composite sintered material is uniform in shape and size. The composite sintered material is formed by a mixture of a hexagonal BN powder having an average particle diameter of not less than 1 .mu.m and an AlN powder having an average particle diameter of about 2 .mu.Type: GrantFiled: October 19, 1989Date of Patent: July 28, 1992Assignee: Hitachi, Ltd.Inventors: Hitoshi Yokono, Takao Terabayashi, Nobuo Kayaba, Takahiro Daikoku, Shigekazu Kieda, Fumiyuki Kobayashi, Shizuo Zushi
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Patent number: 4963974Abstract: The present invention relates to an electroless gold plating solution, a method of plating by using the same, and an electronic device plated with gold by using the same.According to the present electroless gold plating solution, the plating solution components contain no cyanide ions, the amount of a reducing agent used is small, and gold plating can be carried out without causing the gold plating on conducting paths having a fine interval between them to short-circuit the conducting paths.Therefore, according to the method of gold plating by using said electroless gold plating solution, a plating method that is safe in the plating work and in the treatment of its waste liquor can be accomplished. The method has a feature that the method can provide an electronic device on which parts can be mounted highly densely, and wherein the joint reliability to the parts is high.Type: GrantFiled: April 20, 1988Date of Patent: October 16, 1990Assignee: Hitachi, Ltd.Inventors: Jiro Ushio, Osamu Miyazawa, Akira Tomizawa, Hitoshi Yokono, Naoya Kanda, Naoko Matsuura, Setsuo Ando, Hiroaki Okudaira
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Patent number: 4963512Abstract: A method for forming conductor layers of substrates for mounting LSIs and the like and a fabrication method of multilayer substrates are disclosed. These methods comprise steps of forming a metal underlayer having a shape similar to that of a conductor pattern on the substrate, forming an insulation layer over portions of the substrate which are not covered by the metal underlayer, and disposing a plating layer on the metal underlayer by carrying out electroless plating while using the insulation layer as the resist and thereby forming conductors. As compared with a conventional conductor layer forming method, the number of fabrication steps is reduced. And the elimination of the surface grinding step facilitates the fabrication.Type: GrantFiled: December 8, 1988Date of Patent: October 16, 1990Assignee: Hitachi, Ltd.Inventors: Shoichi Iwanaga, Akio Fujiwara, Takayoshi Sowa, Hitoshi Yokono
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Patent number: 4931726Abstract: A semiconductor device testing apparatus which has a plurality of probes and plurality of coaxial cables connected therewith for impedance matching and a plurality of springs for providing flexibility to the individual probes to absorb a level difference in the surface of a semiconductor device.The apparatus constructed in this manner allows for an effective test of a semiconductor device with a high density electrode arrangement.Type: GrantFiled: June 21, 1988Date of Patent: June 5, 1990Assignee: Hitachi, Ltd.Inventors: Susumu Kasukabe, Masasi Ookubo, Yutaka Akiba, Minoru Tanaka, Hitoshi Yokono
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Patent number: 4927044Abstract: Cases for automobile air conditioners or car-loaded refrigerators are molded in an integrated structure of a body part and fixing parts by reaction injection molding from a mixture of a liquid A comprising 20-60% by weight of an aliphatic amine-based polyol, 30-60% by weight of a PO adduct of 4,4'-diaminodiphenylmethane and 15-40% by weight of an ordinary polyol and further containing a foam-controlling agent, a foaming agent and a catalyst and a liquid B comprising polyisocyanate as obtained through impingement.Type: GrantFiled: February 28, 1985Date of Patent: May 22, 1990Assignee: Hitachi, Ltd.Inventors: Masao Gotoh, Yasuo Hira, Kenichi Waragai, Shozo Nakamura, Hitoshi Yokono
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Patent number: 4908696Abstract: The present invention relates to a connector structure for soldering a wiring substrate such as a ceramic wiring substrate to a connector provided on a printed board and also pertains to semiconductor device packages using the same. It is an object of the present invention to provide a connector structure which provides highly reliable electrical connection, together with semiconductor device package using the same. The object is attained by soldering a ceramic wiring substrate to a connector which involves a heater.Type: GrantFiled: September 16, 1987Date of Patent: March 13, 1990Assignee: Hitachi, Ltd.Inventors: Shousaku Ishihara, Hitoshi Yokono, Tsuyoshi Fujita, Ryohei Satoh, Kiyotaka Wasai
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Patent number: 4880464Abstract: An electroless gold plating solution comprising a thiosulfato gold(I) complex, a thiosulfate, thiourea, a pH regulator and a stabilizer. The electroless gold plating solution shows a plating rate and a plating solution stability comparable to those of conventional gold plating solutions containing cyanide ions, and requires a smaller amount of reducing agent to be used therein. Further, the electroless gold plating solution is safe because it does not contain cyanide ions.Type: GrantFiled: January 14, 1988Date of Patent: November 14, 1989Assignee: Hitachi, Ltd.Inventors: Jiro Ushio, Osamu Miyazawa, Hitoshi Yokono, Akira Tomizawa
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Patent number: 4804559Abstract: An electroless gold plating solution comprising a thiosulfato gold(I) complex, a thiosulfate, thiourea, a pH regulator and a stabilizer. The electroless gold plating solution shows a plating rate and a plating solution stability comparable to those of conventional gold plating solutions containing cyanide ions, and requires a smaller amount of reducing agent to be used therein. Further, the electroless gold plating solution is safe because it does not contain cyanide ions.Type: GrantFiled: August 31, 1987Date of Patent: February 14, 1989Assignee: Hitachi, Ltd.Inventors: Jiro Ushio, Osamu Miyazawa, Hitoshi Yokono, Akira Tomizawa
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Patent number: 4753515Abstract: A connector means includes a connector housing provided with a plurality of bores which is defined by a pair of plastic bases each having a plurality of hemicycle grooves each of which has an inner diameter 1 to several .mu.m larger than an outer diameter of each of the optical cables to be connected. After the optical fibres are inserted into the respective bores and secured therein, one end surface of the connector housing is polished. A pair of connected housings are retained so that the polished end surfaces abut on each other thereby to attain a connection between a plurality of optical cables.Type: GrantFiled: June 2, 1986Date of Patent: June 28, 1988Assignee: Hitachi Construction Machinery Co., Ltd.Inventors: Hidemi Sato, Aizo Kaneda, Hitoshi Yokono, Kiichi Suzuki
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Patent number: 4736012Abstract: A semiconductor device containing an .alpha.-rays shielding resin layer on at least active portion of a semiconductor element, said .alpha.-rays shielding resin being a special polyimide resin, is excellent in thermal resistance at the time of sealing the semiconductor element, adhesion of the .alpha.-rays shielding layer to the semiconductor element, and .alpha.-rays shielding ability.Type: GrantFiled: June 29, 1984Date of Patent: April 5, 1988Assignee: Hitachi, Ltd.Inventors: Fusaji Shoji, Akihiro Kenmotsu, Isao Obara, Hitoshi Yokono, Takeshi Komaru
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Patent number: 4715673Abstract: An optical switch having a small number of optical connections includes a substrate in which are provided a first light path for conducting optical signals and a second light path consisting of a photosensitive element and light emitting element in pairs. An optical fiber cable is interrupted by the substrate, and optical signals in the fiber cable are transmitted through the first light path or intervened by an electrical system through the second light path in response to the switching movement of the substrate.Type: GrantFiled: May 1, 1986Date of Patent: December 29, 1987Assignee: Hitachi, Ltd.Inventors: Takanobu Noro, Yasumasa Koakutsu, Tamio Takeuchi, Masao Yano, Seiichi Onoda, Hideo Arima, Hitoshi Yokono, Hirayoshi Tanei
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Patent number: 4643913Abstract: A process for producing solar cells which comprises applying a composition for anti-reflection coating formation on one side of a silicon base plate having a p-n junction therein, printing an Ag paste for contact formation on predetermined areas of the coat, and heat-treating the resulting plate at a temperature of 400.degree. to 900.degree. C. to complete anti-reflection coating and a light-receiving side contact, the process being characterized in that the composition for anti-reflection coating formation contains as essential component, (a) at least one member selected from the metal-organic ligand complex compounds represented by the general formula M(OR.sub.1).sub.n (L).sub.a-n wherein M is a metal selected from Zn, Al, Ga, In, Ti, Zr, Sn, V, Nb, Ta, Mo, and W; R.sub.1 is a C.sub.1 -C.sub.18 alkyl group; L is an organic ligand which forms an non-hydrolyzable bond with the metal ion; a is the valency of the metal M; and n is an integer satisfying 1.ltoreq.Type: GrantFiled: December 28, 1984Date of Patent: February 17, 1987Assignee: Hitachi, Ltd.Inventors: Masaaki Okunaka, Mitsuo Nakatani, Haruhiko Matsuyama, Hitoshi Yokono, Tokio Isogai, Tadashi Saitoh, Kunihiro Matsukuma, Sumiyuki Midorikawa, Satoru Suzuki