Patents by Inventor Hitoshi Yoshikuni

Hitoshi Yoshikuni has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6940148
    Abstract: A semiconductor device is capable of adjusting an input resistance without changing an input terminal capacitance. The capacitance formed by a capacitive wiring and a comb-shaped wiring can be adjusted by changing the length of the capacitive wiring. The resistance between the capacitive wiring and the ground potential can be adjusted by changing the positions of contacts which interconnect the capacitive wiring and a resistive wiring. Since the resistance can be adjusted simply by changing the connections of the contacts, only the input resistance can be adjusted without changing the input terminal capacitance.
    Type: Grant
    Filed: February 13, 2004
    Date of Patent: September 6, 2005
    Assignee: Elpida Memory, Inc.
    Inventor: Hitoshi Yoshikuni
  • Publication number: 20040159941
    Abstract: A semiconductor device is capable of adjusting an input resistance without changing an input terminal capacitance. The capacitance formed by a capacitive wiring and a comb-shaped wiring can be adjusted by changing the length of the capacitive wiring. The resistance between the capacitive wiring and the ground potential can be adjusted by changing the positions of contacts which interconnect the capacitive wiring and a resistive wiring. Since the resistance can be adjusted simply by changing the connections of the contacts, only the input resistance can be adjusted without changing the input terminal capacitance.
    Type: Application
    Filed: February 13, 2004
    Publication date: August 19, 2004
    Applicant: ELPIDA MEMORY, INC
    Inventor: Hitoshi Yoshikuni
  • Patent number: 6093954
    Abstract: A variable delay circuit has plural delay stages connected in series for providing delay time during signal propagation therethrough, and a high resistive delay signal line on a lower level of a multi-layered semiconductor structure and a low resistive breakable signal line on an upper level of the multi-layered semiconductor structure are connected in parallel between two nodes of each delay stage so as to change the total resistance of the delay stage; when a manufacturer decreases the delay time, the low resistive breakable signal line is broken, and the signal is propagated through the high resistive signal line instead of the low resistive breakable signal line.
    Type: Grant
    Filed: September 4, 1998
    Date of Patent: July 25, 2000
    Assignee: NEC Corporation
    Inventor: Hitoshi Yoshikuni