Abstract: A bimetal layer manufacturing method includes the procedure of: forming a first dielectric layer on the surface of a semiconductor substrate which has a first metal layer (conductive layer) of a selected pattern formed thereon; forming a SOG layer on the surface of the first dielectric layer; forming a second dielectric layer; forming required via holes on the foregoing layers until reaching the first metal layer; forming a linear layer from a dielectrics material through PECVD; removing unnecessary linear layer from selected locations through an anisotropic plasma etching process; finally forming a second metal layer on a selected surface of the linear layer where MIM capacitors to be formed, and forming connection plugs in the via openings without generating via hole poison.

Abstract: The present invention relates to an integrated circuit manufacturing method for producing a double-diffused metal-oxide-semiconductor (DMOS), which utilizes a removable spacer method with a self-aligned channel to manufacture an improved DMOS with a reduced parasitic capacitance, and a high-resistance DMOS for a high power application can thus be fabricated also. Via the present invention, a faster switch with more usable operating frequencies can be achieved.