Patents by Inventor Ho-Bin SONG
Ho-Bin SONG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11901967Abstract: Provided is an analog front-end receiver including: a first equalizer including a first block switch configured to receive a first differential signal through a first node, and configured to block the first differential signal in a first operation mode; a second equalizer including a second block switch configured to receive a second differential signal through a second node, and configured to block the second differential signal in the first operation mode; a terminating resistor provided between the first node and the second node, and configured to receive the first differential signal via the first node, and receive the second differential signal via the second node; and a low pass filter configured to receive a third differential signal converted by the terminating resistor from the first differential signal, and configured to receive a fourth differential signal converted by the terminating resistor from the second differential signal.Type: GrantFiled: July 20, 2021Date of Patent: February 13, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Byeong Gyu Park, Jae Hyun Park, Jun Han Bae, Ho-Bin Song
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Patent number: 11733727Abstract: Disclosed is an integrated circuit including a first bias current generating circuit. The first bias current generating circuit includes a first amplifier receiving a reference voltage and a first voltage and amplifying a difference between them to output a first output voltage, a first bias current generator receiving the first output voltage and outputting a first bias current in response to the first output voltage, a variable resistor receiving the first bias current and outputting the first voltage in response to the first bias current and a calibration code, a second bias current generator receiving the first output voltage and outputting a second bias current to a peripheral circuit in response to the first output voltage, and a third bias current generator receiving the first output voltage and outputting a third bias current to an external device through a first pad in response to the first output voltage.Type: GrantFiled: February 25, 2022Date of Patent: August 22, 2023Inventors: Junhan Bae, Gyeongseok Song, Kyeong-Joon Ko, Jaehyun Park, Hajung Park, Ho-Bin Song
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Patent number: 11522736Abstract: An analog front-end receiver including a termination resistor configured to receive first and second differential signals from different data lines, the second differential signal being differential with respect to the first differential signal, an active equalizer configured to receive a first input differential signal through a first input node and a second input differential signal through a second input node, the first and second input differential signals both having an input common mode voltage, the first and second input differential signals being based on the first and second differential signal, respectively, and output first and output differential signals to first and second output nodes, respectfully, the second output differential signal being differential with respect to the first output differential signal, and an input common mode voltage generator configured to adjust the input common mode voltage to be equal to an output common mode voltage of the first output differential signal.Type: GrantFiled: August 30, 2021Date of Patent: December 6, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Byeong Gyu Park, Jun Han Bae, Yun Geun Nam, Jae Hyun Park, Gyeong Seok Song, Ho-Bin Song
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Publication number: 20220334605Abstract: Disclosed is an integrated circuit including a first bias current generating circuit. The first bias current generating circuit includes a first amplifier receiving a reference voltage and a first voltage and amplifying a difference between them to output a first output voltage, a first bias current generator receiving the first output voltage and outputting a first bias current in response to the first output voltage, a variable resistor receiving the first bias current and outputting the first voltage in response to the first bias current and a calibration code, a second bias current generator receiving the first output voltage and outputting a second bias current to a peripheral circuit in response to the first output voltage, and a third bias current generator receiving the first output voltage and outputting a third bias current to an external device through a first pad in response to the first output voltage.Type: ApplicationFiled: February 25, 2022Publication date: October 20, 2022Inventors: JUNHAN BAE, GYEONGSEOK SONG, KYEONG-JOON KO, JAEHYUN PARK, HAJUNG PARK, HO-BIN SONG
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Publication number: 20220141056Abstract: An analog front-end receiver including a termination resistor configured to receive first and second differential signals from different data lines, the second differential signal being differential with respect to the first differential signal, an active equalizer configured to receive a first input differential signal through a first input node and a second input differential signal through a second input node, the first and second input differential signals both having an input common mode voltage, the first and second input differential signals being based on the first and second differential signal, respectively, and output first and output differential signals to first and second output nodes, respectfully, the second output differential signal being differential with respect to the first output differential signal, and an input common mode voltage generator configured to adjust the input common mode voltage to be equal to an output common mode voltage of the first output differential signal.Type: ApplicationFiled: August 30, 2021Publication date: May 5, 2022Applicant: Samsung Electronics Co., Ltd.Inventors: Byeong Gyu PARK, Jun Han BAE, Yun Guen NAM, Jae Hyun PARK, Gyeong Seok SONG, Ho-Bin SONG
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Publication number: 20220109467Abstract: Provided is an analog front-end receiver including: a first equalizer including a first block switch configured to receive a first differential signal through a first node, and configured to block the first differential signal in a first operation mode; a second equalizer including a second block switch configured to receive a second differential signal through a second node, and configured to block the second differential signal in the first operation mode; a terminating resistor provided between the first node and the second node, and configured to receive the first differential signal via the first node, and receive the second differential signal via the second node; and a low pass filter configured to receive a third differential signal converted by the terminating resistor from the first differential signal, and configured to receive a fourth differential signal converted by the terminating resistor from the second differential signal.Type: ApplicationFiled: July 20, 2021Publication date: April 7, 2022Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Byeong Gyu PARK, Jae Hyun PARK, Jun Han BAE, Ho-Bin SONG
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Patent number: 10135605Abstract: A clock data recovery circuit configured to generate frequency step that is uniform regardless of operational conditions of the clock data recovery circuit.Type: GrantFiled: October 26, 2017Date of Patent: November 20, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Byoung-Joo Yoo, Kyung-Seok Song, Ho-Bin Song
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Publication number: 20180183567Abstract: A clock data recovery circuit configured to generate frequency step that is uniform regardless of operational conditions of the clock data recovery circuit.Type: ApplicationFiled: October 26, 2017Publication date: June 28, 2018Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Byoung-Joo YOO, Kyung-Seok SONG, Ho-Bin SONG
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Patent number: 9071237Abstract: A digital duty cycle correction circuit includes a duty cycle controller and a digital duty control code generator. The duty cycle controller generates first and second output clock signals by compensating duty cycles of first and second input clock signals based on a digital duty control code. The digital duty control code generator generates the digital duty control code based on a frequency value obtained by converting duty cycle information of the first output clock signal and the second output clock signal.Type: GrantFiled: March 13, 2014Date of Patent: June 30, 2015Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Cheon-Oh Lee, Tae-Pyeong Kim, Jung-Myung Choi, Sung-Jun Kim, Ho-Bin Song, Han-Kyul Lim
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Patent number: 8941425Abstract: Provided is a semiconductor device for compensating for an internal skew without training with an external device. The semiconductor device includes a signal generating unit configured to generate and output a reference signal, a first receiving unit configured to receive the reference signal and output a first output signal, a second receiving unit configured to receive the reference signal and output a second output signal, a delay unit configured to delay the first output signal by a certain time and output a delayed signal, a sampling unit configured to sample the second output signal based on the delayed signal and output sampling data, and a skew controlling unit configured to control the delaying unit based on the sampling data.Type: GrantFiled: December 20, 2013Date of Patent: January 27, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Ho-Bin Song, Tae-Pyeong Kim, Cheon-Oh Lee
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Publication number: 20140266362Abstract: A digital duty cycle correction circuit includes a duty cycle controller and a digital duty control code generator. The duty cycle controller generates first and second output clock signals by compensating duty cycles of first and second input clock signals based on a digital duty control code. The digital duty control code generator generates the digital duty control code based on a frequency value obtained by converting duty cycle information of the first output clock signal and the second output clock signal.Type: ApplicationFiled: March 13, 2014Publication date: September 18, 2014Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Cheon-Oh LEE, Tae-Pyeong KIM, Jung-Myung CHOI, Sung-Jun KIM, Ho-Bin SONG, Han-Kyul LIM
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Publication number: 20140191788Abstract: Provided is a semiconductor device for compensating for an internal skew without training with an external device. The semiconductor device includes a signal generating unit configured to generate and output a reference signal, a first receiving unit configured to receive the reference signal and output a first output signal, a second receiving unit configured to receive the reference signal and output a second output signal, a delay unit configured to delay the first output signal by a certain time and output a delayed signal, a sampling unit configured to sample the second output signal based on the delayed signal and output sampling data, and a skew controlling unit configured to control the delaying unit based on the sampling data.Type: ApplicationFiled: December 20, 2013Publication date: July 10, 2014Applicant: SAMSUNG ELECTONICS CO., LTD.Inventors: Ho-Bin SONG, Tae-Pyeong KIM, Cheon-Oh LEE