Patents by Inventor Ho-Ching Chen

Ho-Ching Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240101784
    Abstract: A novel additive for recycling thermoset materials, its related recyclable thermoset composition and its application are disclosed. Specifically, the composition of the additive comprises at least one copolymer that has at least one carbamate group, at least one carbonate group and/or at least one urea group, and a number-average molecular weight of the copolymer is between 100 and 50,000 Da.
    Type: Application
    Filed: September 5, 2023
    Publication date: March 28, 2024
    Inventors: Chien-Hsin Wu, Ying-Chi Huang, Ying-Feng Lin, Wen-Chang Chen, Ho-Ching Huang, Ru-Jong Jeng
  • Patent number: 7537991
    Abstract: A method of fabricating a salicided MOS and a one-sided salicided MOS device on a semiconductor substrate. A conformal oxide layer and an organic layer are sequentially formed on first and second MOS devices and the substrate. The first MOS has a first gate structure, a first spacer and first and second doped regions. The second MOS has a second gate structure, a second spacer and third and fourth doped regions. Anisotropic etching is performed to remove part of the organic layer until the oxide layer on the first and the second gate structures is exposed, wherein a remaining organic layer is left above the substrate. The oxide layer on the first and the second gate structures is removed. The remaining organic layer is removed. The oxide layer on the first, second, and third doped regions is removed. Thus, a silicide layer cannot form on the fourth doped region.
    Type: Grant
    Filed: March 18, 2005
    Date of Patent: May 26, 2009
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Dun-Nian Yaung, Sou-Kuo Wu, Ho-Ching Chen
  • Patent number: 7507596
    Abstract: The present invention is CMOS image sensor and its method of fabrication. This invention provides an efficient structure to improve the quantum efficiency of a CMOS image sensor with borderless contact. The image sensor comprises a N-well/P-substrate type photodiode with borderless contact and dielectric structure covering the photodiode region. The dielectric structure is located between the photodiode and the interlevel dielectric (ILD) and is used as a buffer layer for the borderless contact. The method of fabricating a high performance photodiode comprises forming a photodiode in the n-well region of a shallow trench, and embedding a dielectric material between the ILD oxide and the photodiode having a refraction index higher than the ILD oxide.
    Type: Grant
    Filed: February 23, 2006
    Date of Patent: March 24, 2009
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Dun-Nian Yaung, Shou-Gwo Wuu, Ho-Ching Chen, Chien-Hsien Tseng, Jeng-Shyan Lin
  • Patent number: 7038232
    Abstract: The present invention is a CMOS image sensor and its method of fabrication. This invention provides an efficient structure to improve the quantum efficiency of a CMOS image sensor with borderless contact. The image sensor comprises a N-well/P-substrate type photodiode with borderless contact and dielectric structure covering the photodiode region. The dielectric structure is located between the photodiode and the interlevel dielectric (ILD) and is used as a buffer layer for the borderless contact. The method of fabricating a high performance photodiode comprises forming a photodiode in the n-well region of a shallow trench, and embedding a dielectric material between the ILD oxide and the photodiode having a refraction index higher than the ILD oxide.
    Type: Grant
    Filed: September 24, 2003
    Date of Patent: May 2, 2006
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Dun-Nian Yaung, Shou-Gwo Wuu, Ho-Ching Chen, Chien-Hsien Tseng, Jeng-Shyan Lin
  • Patent number: 6897504
    Abstract: A method of fabricating a salicided MOS and a one-sided salicided MOS device on a semiconductor substrate. A conformal oxide layer and an organic layer are sequentially formed on first and second MOS devices and the substrate. The first MOS has a first gate structure, a first spacer and first and second doped regions. The second MOS has a second gate structure, a second spacer and third and fourth doped regions. Anisotropic etching is performed to remove part of the organic layer until the oxide layer on the first and the second gate structures is exposed, wherein a remaining organic layer is left above the substrate. The oxide layer on the first and the second gate structures is removed. The remaining organic layer is removed. The oxide layer on the first, second, and third doped regions is removed. Thus, a silicide layer cannot form on the fourth doped region.
    Type: Grant
    Filed: March 31, 2003
    Date of Patent: May 24, 2005
    Assignee: Taiwan Semiconductor Manufacturing
    Inventors: Dun-Nian Yaung, Sou-Kuo Wu, Ho-Ching Chen