Patents by Inventor Ho-Hsiang Chen

Ho-Hsiang Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230378910
    Abstract: A band-pass filter (BPF) includes first and second windings. The first winding includes first and second terminals, a first outer extending portion extending from the first terminal, a second outer extending portion extending from the second terminal, and a first conductive structure configured to electrically connect the first and second outer extending portions to each other at a location opposite the first and second terminals. The second winding includes third and fourth terminals positioned between the first and second terminals, and a second conductive structure electrically connected to the third and fourth terminals and extending between the first conductive structure and each of the first and second outer extending portions.
    Type: Application
    Filed: July 31, 2023
    Publication date: November 23, 2023
    Inventors: Chi-Hsien LIN, Ho-Hsiang CHEN, Hsien-Yuan LIAO, Tzu-Jin YEH, Ying-Ta LU
  • Publication number: 20230378169
    Abstract: The present disclosure provides a semiconductor device and a method of manufacturing a semiconductor device. The semiconductor device comprises a substrate, a first gate electrode, a second gate electrode, a first doped region, a second doped region, a third doped region, and a first interconnection structure. The substrate comprises a well region of a first conductive type. The first and second gate electrodes are disposed on the substrate. The first, second, and third doped regions are embedded within the well region and are of the first conductive type. The first interconnection structure electrically connects the first gate electrode and the second gate electrode. The first doped region and the second doped region are disposed on opposite sides of the first gate electrode.
    Type: Application
    Filed: May 18, 2022
    Publication date: November 23, 2023
    Inventors: HO-HSIANG CHEN, CHI-HSIEN LIN, YING-TA LU, HSIEN-YUAN LIAO, HSIU-WEN WU, CHIAO-HAN LEE, TZU-JIN YEH
  • Patent number: 11817385
    Abstract: An integrated circuit includes an inductor that includes a first set of conductive lines in a first metal layer, and is over a substrate, and a guard ring. The guard ring includes a first conductive line in a second metal layer, and extending in a first direction, a second conductive line extending in a second direction, and a first staggered line coupled between the first conductive line and the second conductive line. The first staggered line includes a second set of conductive lines in the second metal layer, and extends in the first direction, a third set of conductive lines in a third metal layer, and extends in the second direction, and a first set of vias coupling the second and third set of conductive lines together. All metal lines in the third metal layer that are part of the guard ring extend in the second direction.
    Type: Grant
    Filed: July 30, 2021
    Date of Patent: November 14, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chiao-Han Lee, Chi-Hsien Lin, Ho-Hsiang Chen, Hsien-Yuan Liao, Tzu-Jin Yeh, Ying-Ta Lu
  • Patent number: 11777446
    Abstract: An oscillator includes a forward stage including first and second terminals and a transformer-coupled band-pass filter (BPF) coupled between the first and second terminals and including a coupling device between the first and second terminals, and a transformer including first and second windings in a metal layer of an IC. The first winding includes a first conductive structure coupled to the first terminal and a second conductive structure coupled to a voltage node, a third conductive structure including first and second extending portions connected to the first and second conductive structures. The second winding includes a fourth conductive structure including a third extending portion coupled to the voltage node, and a fourth extending portion coupled to the second terminal. The third extending portion is between the second conductive structure and the first extending portion, and the fourth extending portion is between the first conductive structure and the second extending portion.
    Type: Grant
    Filed: April 25, 2022
    Date of Patent: October 3, 2023
    Inventors: Chi-Hsien Lin, Ho-Hsiang Chen, Hsien-Yuan Liao, Tzu-Jin Yeh, Ying-Ta Lu
  • Publication number: 20230297759
    Abstract: A method of verifying an integrated circuit stack includes adding a first dummy layer to a first contact pad of a circuit, wherein a location of the first dummy layer is determined based on a location of a second contact pad of a connecting substrate. The method further includes converting the first dummy layer location to the connecting substrate. The method further includes adjusting the first dummy layer location in the circuit in response to a determination that the first dummy layer location is misaligned with the second contact pad. The method further includes performing a first layout versus schematic (LVS) check of the connecting substrate including the first dummy layer in response to a determination that the first dummy layer is aligned with the second contact pad.
    Type: Application
    Filed: May 25, 2023
    Publication date: September 21, 2023
    Inventors: Feng Wei KUO, Shuo-Mao CHEN, Chin-Yuan HUANG, Kai-Yun LIN, Ho-Hsiang CHEN, Chewn-Pu JOU
  • Publication number: 20230282644
    Abstract: A cell layout design for an integrated circuit. In one embodiment, the integrated circuit includes a dual-gate cell forming two transistors connected with each other via a common source/drain terminal. The dual-gate cell includes an active region, two gate lines extending across the active region, at least one first gate via disposed on one or both of the two gate lines and overlapped with the active region, and second gate vias disposed on one or both of the two gate lines and located outside the active region.
    Type: Application
    Filed: June 30, 2022
    Publication date: September 7, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ho-Hsiang CHEN, Chi-Hsien LIN, Ying-Ta LU, Hsien-Yuan LIAO, Hsiu-Wen WU, Chiao-Han LEE, Tzu-Jin YEH
  • Patent number: 11740504
    Abstract: A curved panel includes a first curved substrate, a second curved substrate, a curved coverlens, and an adhesive structure. The first curved substrate and the second curved substrate are overlapped with each other. First to fourth sidewalls of the first curved substrate correspond to fifth to eighth sidewalls of the second curved substrate, respectively. The first to third sidewalls of the first curved substrate extend beyond the fifth to seventh sidewalls of the second curved substrate, respectively. The second curved substrate is located between the curved coverlens and the first curved substrate. The second curved substrate is bonded to the curved coverlens through an adhesive layer. The adhesive structure is located between the first curved substrate and the curved coverlens and is laterally located between the first sidewall and the fifth sidewall, between the second sidewall and the sixth sidewall, and between the third sidewall and the seventh sidewall.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: August 29, 2023
    Assignee: AUO Corporation
    Inventors: Chun-Yu Lee, Sheng-Yuan Chiu, Yen-Chang Chen, Po-Shu Huang, Ho-Hsiang Wang
  • Patent number: 11736064
    Abstract: A differential oscillator includes a differential circuit and a transformer-coupled band-pass filter (BPF) coupled between first and second output nodes. The BPF includes a coupling device coupled between the output nodes and a transformer including first and second windings in a metal layer of an IC. The first winding includes first and second conductive structures coupled to the first output node and a voltage node, respectively, and a third conductive structure including first and second extending portions connected to the first and second conductive structures, respectively. The second winding includes a fourth conductive structure including a third extending portion coupled to the voltage node and a fourth extending portion coupled to the second output node. The third extending portion is between the second conductive structure and the first extending portion, and the fourth extending portion is between the first conductive structure and the second extending portion.
    Type: Grant
    Filed: April 28, 2022
    Date of Patent: August 22, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chi-Hsien Lin, Ho-Hsiang Chen, Hsien-Yuan Liao, Tzu-Jin Yeh, Ying-Ta Lu
  • Patent number: 11675957
    Abstract: A method of verifying an integrated circuit stack includes adding a dummy layer to a contact pad of a functional circuit, wherein a location of the dummy layer is determined based on a location of a contact pad of a connecting substrate. The method further includes converting the dummy layer location to the connecting substrate. The method further includes performing a layout versus schematic (LVS) check of the connecting substrate including the dummy layer in response to a determination that the dummy layer is aligned with the contact pad of the connecting substrate.
    Type: Grant
    Filed: May 13, 2021
    Date of Patent: June 13, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Feng Wei Kuo, Shuo-Mao Chen, Chin-Yuan Huang, Kai-Yun Lin, Ho-Hsiang Chen, Chewn-Pu Jou
  • Publication number: 20220300694
    Abstract: A phase shifter includes a first transistor and a second transistor. The first transistor includes a first gate terminal configured to receive a first voltage. The first transistor is configured to adjust at least a resistance or a first capacitance of the phase shifter responsive to the first voltage. The second transistor is coupled to the first transistor. The second transistor includes a second gate terminal configured to receive a second voltage. The second transistor is configured to adjust a second capacitance of the phase shifter responsive to the second voltage. The second gate terminal includes a first polysilicon portion and a second polysilicon portion extending in a first direction. The first polysilicon portion and the second polysilicon portion are positioned along opposite edges of an active region of the first transistor and the second transistor.
    Type: Application
    Filed: June 6, 2022
    Publication date: September 22, 2022
    Inventors: Chi-Hsien LIN, Ho-Hsiang CHEN, Hsien-Yuan LIAO, Tzu-Jin YEH, Ying-Ta LU
  • Patent number: 11450769
    Abstract: Semiconductor structures and methods for forming a semiconductor structure are provided. An active semiconductor region is disposed in a substrate. A gate is formed over the substrate. Source and drain regions of a transistor are formed in the active semiconductor region on opposite sides of the gate. The drain region has a first width, and the source region has a second width that is not equal to the first width.
    Type: Grant
    Filed: February 24, 2021
    Date of Patent: September 20, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Hsien-Yuan Liao, Chien-Chih Ho, Chi-Hsien Lin, Hua-Chou Tseng, Ho-Hsiang Chen, Ru-Gun Liu, Tzu-Jin Yeh, Ying-Ta Lu
  • Publication number: 20220263464
    Abstract: An oscillator includes a forward stage including first and second terminals and a transformer-coupled band-pass filter (BPF) coupled between the first and second terminals and including a coupling device between the first and second terminals, and a transformer including first and second windings in a metal layer of an IC. The first winding includes a first conductive structure coupled to the first terminal and a second conductive structure coupled to a voltage node, a third conductive structure including first and second extending portions connected to the first and second conductive structures. The second winding includes a fourth conductive structure including a third extending portion coupled to the voltage node, and a fourth extending portion coupled to the second terminal. The third extending portion is between the second conductive structure and the first extending portion, and the fourth extending portion is between the first conductive structure and the second extending portion.
    Type: Application
    Filed: April 25, 2022
    Publication date: August 18, 2022
    Inventors: Chi-Hsien LIN, Ho-Hsiang CHEN, Hsien-Yuan LIAO, Tzu-Jin YEH, Ying-Ta LU
  • Publication number: 20220255504
    Abstract: A differential oscillator includes a differential circuit and a transformer-coupled band-pass filter (BPF) coupled between first and second output nodes. The BPF includes a coupling device coupled between the output nodes and a transformer including first and second windings in a metal layer of an IC. The first winding includes first and second conductive structures coupled to the first output node and a voltage node, respectively, and a third conductive structure including first and second extending portions connected to the first and second conductive structures, respectively. The second winding includes a fourth conductive structure including a third extending portion coupled to the voltage node and a fourth extending portion coupled to the second output node. The third extending portion is between the second conductive structure and the first extending portion, and the fourth extending portion is between the first conductive structure and the second extending portion.
    Type: Application
    Filed: April 28, 2022
    Publication date: August 11, 2022
    Inventors: Chi-Hsien LIN, Ho-Hsiang CHEN, Hsien-Yuan LIAO, Tzu-Jin YEH, Ying-Ta LU
  • Patent number: 11354481
    Abstract: A phase shifter includes an active region, a first and a second set of gates and a set of contacts. The active region extends in a first direction and is located at a first level. The first and second set of gates each extend in a second direction, overlap the active region and are located at a second level. The second set of gates are positioned along opposite edges of the active region, are configured to receive a first voltage, and are part of a first transistor. The first transistor is configured to adjust a first capacitance of the phase shifter responsive to the first voltage. The set of contacts extend in the second direction, are over the active region, are located at a third level, and are positioned between at least the second set of gates.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: June 7, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chi-Hsien Lin, Ho-Hsiang Chen, Hsien-Yuan Liao, Tzu-Jin Yeh, Ying-Ta Lu
  • Patent number: 11323068
    Abstract: In some embodiments, a differential oscillator includes a differential circuit coupled between a first output node and a second output node and a transformer-coupled band-pass filter (BPF). The transformer-coupled BPF is coupled between the first output node and the second output node and includes a coupling device and a transformer. The coupling device is coupled between the first output node and the second output node. The transformer includes a first winding coupled between the first output node and a voltage node and a second winding coupled between the second output node and the voltage node.
    Type: Grant
    Filed: April 15, 2021
    Date of Patent: May 3, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chi-Hsien Lin, Ho-Hsiang Chen, Hsien-Yuan Liao, Tzu-Jin Yeh, Ying-Ta Lu
  • Patent number: 11316473
    Abstract: A band-pass filter (BPF) includes a pair of coupled transformers including first through fourth conductive structures. The first conductive structure includes a first terminal and two first extending portions extending from the first terminal and configured as primary windings. The second conductive structure includes a second terminal and two second extending portions extending from the second terminal. A first via connects the third conductive structure to a first one of the two second extending portions, the third conductive structure and the first one of the two second extending portions thereby being configured as a first secondary winding. A second via connects the fourth conductive structure to a second one of the two second extending portions, the fourth conductive structure and the second one of the two second extending portions thereby being configured as a second secondary winding.
    Type: Grant
    Filed: February 11, 2021
    Date of Patent: April 26, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chi-Hsien Lin, Ho-Hsiang Chen, Hsien-Yuan Liao, Tzu-Jin Yeh, Ying-Ta Lu
  • Publication number: 20210358844
    Abstract: An integrated circuit includes an inductor that includes a first set of conductive lines in a first metal layer, and is over a substrate, and a guard ring. The guard ring includes a first conductive line in a second metal layer, and extending in a first direction, a second conductive line extending in a second direction, and a first staggered line coupled between the first conductive line and the second conductive line. The first staggered line includes a second set of conductive lines in the second metal layer, and extends in the first direction, a third set of conductive lines in a third metal layer, and extends in the second direction, and a first set of vias coupling the second and third set of conductive lines together. All metal lines in the third metal layer that are part of the guard ring extend in the second direction.
    Type: Application
    Filed: July 30, 2021
    Publication date: November 18, 2021
    Inventors: Chiao-Han LEE, Chi-Hsien LIN, Ho-Hsiang CHEN, Hsien-Yuan LIAO, Tzu-Jin YEH, Ying-Ta LU
  • Patent number: 11145767
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a floating substrate; and a capacitor grounded and connected to the floating substrate. A method of manufacturing a semiconductor structure is also provided.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: October 12, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsiao-Tsung Yen, Yu-Ling Lin, Chin-Wei Kuo, Ho-Hsiang Chen, Chewn-Pu Jou, Min-Chie Jeng
  • Publication number: 20210264094
    Abstract: A method of verifying an integrated circuit stack includes adding a dummy layer to a contact pad of a functional circuit, wherein a location of the dummy layer is determined based on a location of a contact pad of a connecting substrate. The method further includes converting the dummy layer location to the connecting substrate. The method further includes performing a layout versus schematic (LVS) check of the connecting substrate including the dummy layer in response to a determination that the dummy layer is aligned with the contact pad of the connecting substrate.
    Type: Application
    Filed: May 13, 2021
    Publication date: August 26, 2021
    Inventors: Feng Wei KUO, Shuo-Mao CHEN, Chin-Yuan HUANG, Kai-Yun LIN, Ho-Hsiang CHEN, Chewn-Pu JOU
  • Patent number: 11081444
    Abstract: An integrated circuit includes an inductor over a substrate and a guard ring surrounding the inductor. The guard ring includes a first staggered line, a first metal line extending in a first direction and a second metal line extending in a second direction different from the first direction. The first staggered line has a first end coupled to the first metal line, and a second end coupled to the second metal line. The first staggered line includes a first set of vias, a first set of metal lines in a first metal layer and a second set of metal lines in a second metal layer different from the first metal layer. The first set of vias coupling the first set of metal lines with the second of second metal lines.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: August 3, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chiao-Han Lee, Hsien-Yuan Liao, Ying-Ta Lu, Chi-Hsien Lin, Ho-Hsiang Chen, Tzu-Jin Yeh