Abstract: A semiconductor device includes a substrate including a cell block region and a peripheral region adjacent to each other in a first direction, first and second active patterns adjacent to each other in a second direction that is different from the first direction on the cell block region, a first bit line extending in the first direction on the first active pattern, a second bit line extending in the first direction on the second active pattern, a bit line connector connecting the first bit line and the second bit line to each other and adjacent to the peripheral region, an inner spacer on an inner surface of the bit line connector, and an outer spacer on an outer surface of the bit line connector. The inner spacer extends on (e.g., covers) the inner surface of the bit line connector and extends onto (e.g., continuously extends onto) inner surfaces of the first bit line and the second bit line.

Abstract: A semiconductor device may include a substrate including a core region, a cell block region, and a peripheral region, which are sequentially arranged in a first direction, and a bit line structure on the cell block region. The bit line structure may include a first bit line and a second bit line, which extend in the first direction and are adjacent to each other in a second direction crossing the first direction, a bit line connector, which electrically connects the first bit line to the second bit line and is adjacent to the peripheral region, and a bit line pad, which is electrically connected to the first bit line and is adjacent to the core region.

Abstract: A memory device includes a substrate having first and second active patterns adjacent to each other and separated by a trench, the first and second active patterns including a first source/drain region; the second active pattern includes a second source/drain region. The second source/drain region includes first and second sidewall surfaces adjacent the first source/drain region and a connecting surface that connects the first and second sidewall surfaces. The second sidewall surface is set back from the first sidewall surface. An isolation layer is included in the trench and on the first sidewall surface. A bit line includes a contact part connected to the first source/drain region. A contact is coupled to the second source/drain region with a lower spacer between the contact and the contact part of the bit line, a landing pad on the contact, and a data storage element on the landing pad.

Abstract: A semiconductor device may include a substrate including trenches and contact recesses having a curved surface profile, conductive patterns in the trenches, buried contacts including first portions filling the contact recesses and second portions on the first portions, and spacer structures including first and second spacers. The second portions may have a pillar shape and a smaller width than top surfaces of the first portions. The buried contacts may be spaced apart from the conductive patterns by the spacer structures. The first spacers may be on the first portions of the buried contacts at outermost parts of the spacer structures. The first spacers may extend along the second portions of the buried contacts and contact the buried contacts. The second spacers may extend along the side surfaces of the conductive patterns and the trenches. The second spacers may contact the conductive patterns. The first spacers may include silicon oxide.

Abstract: A semiconductor device includes a semiconductor substrate including a trench, a direct contact in the trench, the direct contact having a width smaller than a width of the trench, a bit line structure on the direct contact, the bit line structure having a width smaller than the width of the trench, a first spacer including a first portion and a second portion, the first portion extending along an entire side surface of the direct contact, and the second portion extending along the trench, a second spacer on the first spacer, the second spacer filling the trench, a third spacer on the second spacer, and an air spacer on the third spacer, the air spacer being spaced apart from the second spacer by the third spacer, wherein the first spacer includes silicon oxide.

Abstract: A semiconductor device includes a substrate having a trench, a conductive pattern in the trench, a spacer structure on a side surface of the conductive pattern, and a buried contact including a first portion apart from the conductive pattern by the spacer structure and filling a contact recess, and a second portion on the first portion having a pillar shape with a width smaller than that of a top surface of the first portion. The spacer structure includes a first spacer extending along the second portion of the buried contact on the first portion of the buried contact and contacting the buried contact, a second spacer extending along the first spacer, and a third spacer extending along the side surface of the conductive pattern and the trench and apart from the first spacer by the second spacer, the first spacer includes silicon oxide, and the second spacer includes silicon nitride.

Abstract: A semiconductor device includes a substrate including a cell region and a peripheral region, a cell gate electrode buried in a groove crossing a cell active portion of the cell region, a cell line pattern crossing over the cell gate electrode, the cell line pattern being connected to a first source/drain region in the cell active portion at a side of the cell gate electrode, a peripheral gate pattern crossing over a peripheral active portion of the peripheral region, a planarized interlayer insulating layer on the substrate around the peripheral gate pattern, and a capping insulating layer on the planarized interlayer insulating layer and a top surface of the peripheral gate pattern, the capping insulating layer including an insulating material having an etch selectivity with respect to the planarized interlayer insulating layer.

Abstract: A semiconductor device includes a semiconductor substrate including a trench, a direct contact in the trench, the direct contact having a width smaller than a width of the trench, a bit line structure on the direct contact, the bit line structure having a width smaller than the width of the trench, a first spacer including a first portion and a second portion, the first portion extending along an entire side surface of the direct contact, and the second portion extending along the trench, a second spacer on the first spacer, the second spacer filling the trench, a third spacer on the second spacer, and an air spacer on the third spacer, the air spacer being spaced apart from the second spacer by the third spacer, wherein the first spacer includes silicon oxide.

Abstract: A semiconductor device includes a substrate having a trench, a conductive pattern in the trench, a spacer structure on a side surface of the conductive pattern, and a buried contact including a first portion apart from the conductive pattern by the spacer structure and filling a contact recess, and a second portion on the first portion having a pillar shape with a width smaller than that of a top surface of the first portion. The spacer structure includes a first spacer extending along the second portion of the buried contact on the first portion of the buried contact and contacting the buried contact, a second spacer extending along the first spacer, and a third spacer extending along the side surface of the conductive pattern and the trench and apart from the first spacer by the second spacer, the first spacer includes silicon oxide, and the second spacer includes silicon nitride.

Abstract: A semiconductor device may include a substrate including trenches and contact recesses having a curved surface profile, conductive patterns in the trenches, buried contacts including first portions filling the contact recesses and second portions on the first portions, and spacer structures including first and second spacers. The second portions may have a pillar shape and a smaller width than top surfaces of the first portions. The buried contacts may be spaced apart from the conductive patterns by the spacer structures. The first spacers may be on the first portions of the buried contacts at outermost parts of the spacer structures. The first spacers may extend along the second portions of the buried contacts and contact the buried contacts. The second spacers may extend along the side surfaces of the conductive patterns and the trenches. The second spacers may contact the conductive patterns. The first spacers may include silicon oxide.

Abstract: A semiconductor device includes a substrate including a cell region and a peripheral region, a cell gate electrode buried in a groove crossing a cell active portion of the cell region, a cell line pattern crossing over the cell gate electrode, the cell line pattern being connected to a first source/drain region in the cell active portion at a side of the cell gate electrode, a peripheral gate pattern crossing over a peripheral active portion of the peripheral region, a planarized interlayer insulating layer on the substrate around the peripheral gate pattern, and a capping insulating layer on the planarized interlayer insulating layer and a top surface of the peripheral gate pattern, the capping insulating layer including an insulating material having an etch selectivity with respect to the planarized interlayer insulating layer.

Abstract: A semiconductor device includes a substrate including a cell region and a peripheral region, a cell gate electrode buried in a groove crossing a cell active portion of the cell region, a cell line pattern crossing over the cell gate electrode, the cell line pattern being connected to a first source/drain region in the cell active portion at a side of the cell gate electrode, a peripheral gate pattern crossing over a peripheral active portion of the peripheral region, a planarized interlayer insulating layer on the substrate around the peripheral gate pattern, and a capping insulating layer on the planarized interlayer insulating layer and a top surface of the peripheral gate pattern, the capping insulating layer including an insulating material having an etch selectivity with respect to the planarized interlayer insulating layer.

Abstract: A semiconductor device includes a substrate including a cell region and a peripheral region, a cell gate electrode buried in a groove crossing a cell active portion of the cell region, a cell line pattern crossing over the cell gate electrode, the cell line pattern being connected to a first source/drain region in the cell active portion at a side of the cell gate electrode, a peripheral gate pattern crossing over a peripheral active portion of the peripheral region, a planarized interlayer insulating layer on the substrate around the peripheral gate pattern, and a capping insulating layer on the planarized interlayer insulating layer and a top surface of the peripheral gate pattern, the capping insulating layer including an insulating material having an etch selectivity with respect to the planarized interlayer insulating layer.

Abstract: A semiconductor device includes a substrate having an active region defined by a device isolation layer and at least a gate trench linearly extending in a first direction to cross the active region, the active region having a gate area at a bottom of the gate trench and a junction area at a surface of the substrate. The device further may include a first conductive line filling the gate trench and extending in the first direction, the first conductive line having a buried gate structure on the gate area of the active region. The device also may include a junction including implanted dopants at the junction area of the active region, and a junction separator on the device isolation layer and defining the junction. The junction separator may be formed of an insulative material and have an etch resistance greater than that of the device isolation layer.

Abstract: A semiconductor device includes a substrate having an active region defined by a device isolation layer and at least a gate trench linearly extending in a first direction to cross the active region, the active region having a gate area at a bottom of the gate trench and a junction area at a surface of the substrate. The device further may include a first conductive line filling the gate trench and extending in the first direction, the first conductive line having a buried gate structure on the gate area of the active region. The device also may include a junction including implanted dopants at the junction area of the active region, and a junction separator on the device isolation layer and defining the junction. The junction separator may be formed of an insulative material and have an etch resistance greater than that of the device isolation layer.

Abstract: A semiconductor device includes a substrate having an active region defined by a device isolation layer and at least a gate trench linearly extending in a first direction to cross the active region, the active region having a gate area at a bottom of the gate trench and a junction area at a surface of the substrate. The device further may include a first conductive line filling the gate trench and extending in the first direction, the first conductive line having a buried gate structure on the gate area of the active region. The device also may include a junction including implanted dopants at the junction area of the active region, and a junction separator on the device isolation layer and defining the junction. The junction separator may be formed of an insulative material and have an etch resistance greater than that of the device isolation layer.

Abstract: A semiconductor device includes a substrate having an active region defined by a device isolation layer and at least a gate trench linearly extending in a first direction to cross the active region, the active region having a gate area at a bottom of the gate trench and a junction area at a surface of the substrate. The device further may include a first conductive line filling the gate trench and extending in the first direction, the first conductive line having a buried gate structure on the gate area of the active region. The device also may include a junction including implanted dopants at the junction area of the active region, and a junction separator on the device isolation layer and defining the junction. The junction separator may be formed of an insulative material and have an etch resistance greater than that of the device isolation layer.

Abstract: Provided are semiconductor integrated circuit (IC) devices including gate patterns having a step difference therebetween and a connection line interposed between the gate patterns. The semiconductor IC device includes a semiconductor substrate including a peripheral active region, a cell active region, and a device isolation layer. Cell gate patterns are disposed on the cell active region and the device isolation layer. A peripheral gate pattern is disposed on the peripheral active region. A cell electrical node is disposed on the cell active region adjacent to the cell gate patterns. Peripheral electrical nodes are disposed on the peripheral active region adjacent to the peripheral gate pattern. Connection lines are disposed on the cell gate patterns disposed on the device isolation layer. The connection lines are connected between the cell gate patterns and the peripheral gate pattern.

Abstract: A semiconductor device includes a substrate including a cell region and a peripheral region, a cell gate electrode buried in a groove crossing a cell active portion of the cell region, a cell line pattern crossing over the cell gate electrode, the cell line pattern being connected to a first source/drain region in the cell active portion at a side of the cell gate electrode, a peripheral gate pattern crossing over a peripheral active portion of the peripheral region, a planarized interlayer insulating layer on the substrate around the peripheral gate pattern, and a capping insulating layer on the planarized interlayer insulating layer and a top surface of the peripheral gate pattern, the capping insulating layer including an insulating material having an etch selectivity with respect to the planarized interlayer insulating layer.

Abstract: A semiconductor device includes a substrate including a cell region and a peripheral region, a cell gate electrode buried in a groove crossing a cell active portion of the cell region, a cell line pattern crossing over the cell gate electrode, the cell line pattern being connected to a first source/drain region in the cell active portion at a side of the cell gate electrode, a peripheral gate pattern crossing over a peripheral active portion of the peripheral region, a planarized interlayer insulating layer on the substrate around the peripheral gate pattern, and a capping insulating layer on the planarized interlayer insulating layer and a top surface of the peripheral gate pattern, the capping insulating layer including an insulating material having an etch selectivity with respect to the planarized interlayer insulating layer.