Patents by Inventor Ho J. Lee

Ho J. Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5565084
    Abstract: Disclosed are electropolishing methods for etching a substrate in self alignment. A hole is formed in a substrate in self alignment by using an electropolishing system, wherein a reaction tube, an etchant solution, an electrode, a constant current source and the silicon substrate, said etchant solution being contained in a space confined by the reaction tube and the substrate, which is attached to one end of the reaction tube in such a way that the bottom of the substrate may be toward the interior of the space, said constant current source being connected with a metal layer formed on the substrate and the electrode. The substrate is made to be porous by flowing a constant current and etched by the action of the etchant solution while breaking the current. In addition to being economical, the methods can determine the position and size of the hole accurately and precisely. Further, neither chemical damage nor mechanical impact is generated on the substrate.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: October 15, 1996
    Assignee: Qnix Computer Co., Ltd.
    Inventors: Ho J. Lee, Hi D. Lee, Jae D. Lee, Jun B. Yoon, Chul H. Han, Choong K. Kim, Doo W. Seo
  • Patent number: 5561639
    Abstract: Disclosed is a semiconductor memory device carrying out reading and writing operations of data, comprising memory means consisting of a plurality of memory cells for storing data; test signal generation means for generating a test signal upon a test being carried out; at least one first buffer for receiving an external address bit and generating inverting and noninverting address bits; at least one second address buffer for selectively receiving said external address bit in response to said test signal from said test signal generation means and generating said inverting and noninverting address bits or the signals of the same logic value through two output terminals thereof; decoding means for receiving output signals from said first and second address buffers and selecting one or plural corresponding memory cells of said memory means; and voltage level compensation means for compensating a voltage level applied to each of words lines of said memory cells selected by said decoding means in accordance with sai
    Type: Grant
    Filed: August 22, 1995
    Date of Patent: October 1, 1996
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventors: Kyoung S. Lee, Kang C. Lee, Kyeong J. Jang, Kwang Y. Chung, Ho J. Lee, Huy C. Bae
  • Patent number: 5245589
    Abstract: A method and apparatus for processing a set of signals to identify narrow bandwidth features of the signals, and optionally to process the signals further to extract information about the identified narrow-band features. The invention processes a set of input signal frames (a two-dimensional pixel array) to generate a narrow-band feature signal (also a two-dimensional pixel array) from which narrow-band features of the input signal frames can be efficiently, automatically, and unambiguously identified. In a class of preferred embodiments, the input signal frames are the power spectra of a set of sequentially measured signals. Thus, the set of input signal frames is a "spectrogram," comprising rows and columns of pixels (with row indices representing time, and column indices representing frequency). Alternatively, the input signal frames represent a data array of another type, such as a correlogram or a sequence of images.
    Type: Grant
    Filed: March 20, 1992
    Date of Patent: September 14, 1993
    Inventors: Jonathan S. Abel, Ho J. Lee