Abstract: A method of and testing jig for sequentially testing front and rear surfaces of a semiconductor chip is shown. The testing jig includes a support package having a first cavity over which the semiconductor chip mounts; an infrared filter affixed relative to the first cavity and attached to a rear surface of the semiconductor chip; and a test substrate having a second cavity exposing the infrared filter and upon which the support package mounts. Front and rear surfaces of the semiconductor chip can be conveniently and sequentially tested. Because the testing jig includes the infrared filter and the heat pad, heat can be easily transmitted to the detective chip.

Abstract: A device and method of manufacturing a fuse region are disclosed. The fuse region may include an interlayer insulating layer formed on a substrate, a plurality of fuses disposed on the interlayer insulating layer, and fuse isolation walls located between the fuses, wherein each of the fuse isolation walls may include lower and upper fuse isolation patterns.

Abstract: A laser link structure used in semiconductor devices and a fuse box using the laser link structure preferably include a plurality of first conductive line patterns positioned in parallel at predetermined intervals, and a second conductive line pattern broadly formed on the plurality of first conductive line patterns for forming hole regions which link the second conductive line pattern to the plurality of first conductive line patterns. Preferably, at least one hole region is formed on each of the plurality of first conductive line patterns, and via holes are formed in the hole regions.

Abstract: A fuse box including make-links and a redundancy address decoder including the fuse box are provided. It is preferable that the fuse box includes a plurality of make-links for programming an address of a defective normal memory cell with an address of a corresponding redundant memory cell, and the address is a row address or a column address. The redundant address decoder includes a fuse box having a plurality of make-links for decoding an address of a defect cell and a redundant word line selection circuit for selecting a word line of a redundant cell corresponding to the address of the defect cell in response to a signal output from the fuse box.

Abstract: The invention relates to a fuse layout structure in a laser fuse box of a semiconductor integrated circuit and a method for fabricating the same. In one example of the invention, the fuse layout structure in a laser fuse box of the semiconductor integrated circuit includes a plurality of fuses with the central regions thereof extending parallel to each other within the fuse box, and the central regions of the fuses being covered with an insulative protection layer. Thus, the fuse layout structure of the present invention occupies a minimum area in the chip while minimizing influences of the heat generated by fusing neighboring fuses.

Abstract: The invention relates to a fuse layout structure in a laser fuse box of a semiconductor integrated circuit and a method for fabricating the same. In one embodiment of the invention, the fuse layout structure in a laser fuse box of the semiconductor integrated circuit comprises a plurality of fuses with the central regions thereof extending parallel to each other within the fuse box, and the central regions of the fuses being covered with an insulative protection layer. Thus, the fuse layout structure of the present invention occupies a minimum area in the chip while minimizing influences of the heat generated by fusing neighboring fuses.

Abstract: A laser link structure used in semiconductor devices and a fuse box using the laser link structure preferably include a plurality of first conductive line patterns positioned in parallel at predetermined intervals, and a second conductive line pattern broadly formed on the plurality of first conductive line patterns for forming hole regions which link the second conductive line pattern to the plurality of first conductive line patterns. Preferably, at least one hole region is formed on each of the plurality of first conductive line patterns, and via holes are formed in the hole regions.

Abstract: A fuse layout structure in a laser fuse box of a semiconductor integrated circuit and a method for fabricating the same. In one embodiment of the invention, the fuse layout structure in a laser fuse box of the semiconductor integrated circuit comprises a plurality of fuses with the central regions thereof extending parallel to each other within the fuse box, and the central regions of the fuses being covered with an insulative protection layer. Thus, the fuse layout structure of the present invention occupies a minimum area in the chip while minimizing influences of the heat generated by fusing neighboring fuses.

Abstract: A fuse box including make-links and a redundancy address decoder including the fuse box are provided. It is preferable that the fuse box includes a plurality of make-links for programming an address of a defective normal memory cell with an address of a corresponding redundant memory cell, and the address is a row address or a column address. The redundant address decoder includes a fuse box having a plurality of make-links for decoding an address of a defect cell and a redundant word line selection circuit for selecting a word line of a redundant cell corresponding to the address of the defect cell in response to a signal output from the fuse box.