Abstract: A gate line extending in a horizontal direction is formed on an insulating substrate, and a data line is formed perpendicular to the gate line defining a pixel of a matrix array. Pixel electrodes receiving image signals through the data line are formed in a pixel, and a thin film transistor having a gate electrode connected to the gate line, a source electrode connected to the data line, and a drain electrode connected to the pixel electrode is formed on the portion where the gate lines and the data lines intersect. A storage wire including a storage electrode line in the horizontal direction, a storage electrode connected to the storage electrode line, and at least one of the storage electrode connection portions connecting storage electrodes of neighboring pixels is formed in the same direction as the gate line.

Abstract: A gate line extending in a horizontal direction is formed on an insulating substrate, and a data line is formed perpendicular to the gate line defining a pixel of a matrix array. Pixel electrodes receiving image signals through the data line are formed in a pixel, and a thin film transistor having a gate electrode connected to the gate line, a source electrode connected to the data line, and a drain electrode connected to the pixel electrode is formed on the portion where the gate lines and the data lines intersect. A storage wire including a storage electrode line in the horizontal direction, a storage electrode connected to the storage electrode line, and at least one of the storage electrode connection portions connecting storage electrodes of neighboring pixels is formed in the same direction as the gate line.

Abstract: A gate line extending in a horizontal direction is formed on an insulating substrate, and a data line is formed perpendicular to the gate line defining a pixel of a matrix array. Pixel electrodes receiving image signals through the data line are formed in a pixel, and a thin film transistor having a gate electrode connected to the gate line, a source electrode connected to the data line, and a drain electrode connected to the pixel electrode is formed on the portion where the gate lines and the data lines intersect. A storage wire including a storage electrode line in the horizontal direction, a storage electrode connected to the storage electrode line, and at least one of the storage electrode connection portions connecting storage electrodes of neighboring pixels is formed in the same direction as the gate line.

Abstract: A signal processing system of a multiplexed FBG sensor using CDMA comprises a pseudo random bit sequences (PRBS) generator for generating pseudo random bit sequence; a LED for light-emitting at a pseudo random bit from the PRBS generator; a fiber coupler fro transmitting a light signal from the LED into a FBG sensor portion and passing signals reflected by the FBG sensor portion therethrough; the FBG sensor portion for receiving/reflecting the light signal via an optic fiber to forward it back to the fiber coupler; an FBG filter portion for filtering the signal reflected by the FBG sensor portion and passed through the fiber coupler; a photo detector for converting the light signal from the FBG filter portion into the electrical signal; a delaying portion for delaying a pseudo random bit signal from the PRBS generator for a predetermined time period; a mixing portion for mixing the delay signal from the delaying portion and the output signal from the photo detector; and at least one auto-correlation device fo