Abstract: A semiconductor memory device including: a substrate including a cell array region and a boundary region; a first recess region at an upper portion of the substrate in the cell array region; a first bit line extending onto the boundary region and crossing the first recess region; a bit line contact in the first recess region and contacting the first bit line; a second bit line spaced apart from the first recess region and adjacent to the first bit line, the second bit line crossing the cell array region and the boundary region; a cell buried insulation pattern between a side surface of the first bit line contact and an inner wall of the first recess region; and a boundary buried insulation pattern covering sidewalls of the first bit line and the second bit line in the boundary region and including a same material as the cell buried insulation pattern.

Abstract: A semiconductor memory device including: a substrate including a cell array region and a boundary region; a first recess region at an upper portion of the substrate in the cell array region; a first bit line extending onto the boundary region and crossing the first recess region; a bit line contact in the first recess region and contacting the first bit line; a second bit line spaced apart from the first recess region and adjacent to the first bit line, the second bit line crossing the cell array region and the boundary region; a cell buried insulation pattern between a side surface of the first bit line contact and an inner wall of the first recess region; and a boundary buried insulation pattern covering sidewalls of the first bit line and the second bit line in the boundary region and including a same material as the cell buried insulation pattern.

Abstract: A fuse structure, an e-fuse including the fuse structure and a semiconductor device including the e-fuse are disclosed. The fuse structure includes first and second electrodes extending in a first direction, and spaced a predetermined distance apart from each other and having one ends thereof facing each other, an insulation layer formed between the one end of the first electrode and the one end of the second electrode facing each other, and a conductive film overlapping portions of the first and second electrodes on the insulation layer and contacting the first electrode and the one end of the second electrode.

Abstract: A semiconductor device includes a fuse having the form of a capacitor. The semiconductor device includes a cathode formed on a semiconductor substrate, an anode formed over the cathode, and at least one filament having a cylindrical-shell shape formed between the cathode and the anode and electrically connecting the cathode and the anode.

Abstract: A memory device includes an insulation layer, an active pattern, a gate insulation layer and a gate electrode. The insulation layer is formed on a substrate. The active pattern is formed on the insulation layer, and includes two protrusions and a recess between the protrusions. The active pattern includes a first impurity region and a second impurity region at upper portions of the protrusions distal from the substrate, respectively, and a base region at the other portions serving as a floating body for storing data. The gate insulation layer is formed on a surface of the active pattern. The gate electrode is formed on the gate insulation layer, and surrounds a lower portion of the active pattern and partially fills the recess.

Abstract: A fuse structure, an e-fuse including the fuse structure and a semiconductor device including the e-fuse are disclosed. The fuse structure includes first and second electrodes extending in a first direction, and spaced a predetermined distance apart from each other and having one ends thereof facing each other, an insulation layer formed between the one end of the first electrode and the one end of the second electrode facing each other, and a conductive film overlapping portions of the first and second electrodes on the insulation layer and contacting the first electrode and the one end of the second electrode.

Abstract: A method of fabricating a semiconductor device having a capacitorless one-transistor memory cell includes forming a first floating body pattern on a lower insulating layer of a substrate and a first gate pattern crossing over the first floating body pattern and covering sidewalls of the first floating body pattern is formed. The first floating body pattern at both sides of the first gate pattern is partially etched to form a protrusion portion extending between and above the partially etched regions, and first impurity regions are formed in the partially etched regions of the first floating body pattern.

Abstract: A semiconductor device includes a fuse having the form of a capacitor. The semiconductor device includes a cathode formed on a semiconductor substrate, an anode formed over the cathode, and at least one filament having a cylindrical-shell shape formed between the cathode and the anode and electrically connecting the cathode and the anode.

Abstract: In a semiconductor device and a method of manufacturing the semiconductor device, lower electrodes having cylindrical shapes are provided to be arranged repeatedly on a substrate. Upper surfaces of the lower electrodes are flat so that the lower electrodes have uniform heights. Supporting structures are provided between the lower electrodes to support the lower electrode, the supporting structure partially contacting outer surfaces of sidewalls of the lower electrodes that are arranged in a line. A dielectric layer is formed on surfaces of the lower electrodes and the supporting structures. An upper electrode is provided on the dielectric layer. The semiconductor device includes a capacitor having an improved capacitance. Further, the capacitor includes the support structure between the lower electrodes to prevent the adjacent lower electrodes from being short each other.

Abstract: A memory device includes an insulation layer, an active pattern, a gate insulation layer and a gate electrode. The insulation layer is formed on a substrate. The active pattern is formed on the insulation layer, and includes two protrusions and a recess between the protrusions. The active pattern includes a first impurity region and a second impurity region at upper portions of the protrusions distal from the substrate, respectively, and a base region at the other portions serving as a floating body for storing data. The gate insulation layer is formed on a surface of the active pattern. The gate electrode is formed on the gate insulation layer, and surrounds a lower portion of the active pattern and partially fills the recess.

Abstract: A method of fabricating a semiconductor device having a capacitorless one-transistor memory cell includes forming a first floating body pattern on a lower insulating layer of a substrate and a first gate pattern crossing over the first floating body pattern and covering sidewalls of the first floating body pattern is formed. The first floating body pattern at both sides of the first gate pattern is partially etched to form a protrusion portion extending between and above the partially etched regions, and first impurity regions are formed in the partially etched regions of the first floating body pattern.

Abstract: Dynamic random access memory (DRAM) devices including an insulating layer on a semiconductor substrate; a silicon layer on the insulating layer; an active region in the silicon layer; and a unit cell of a transistor on the active region are provided. The DRAM device does not include a capacitor.