Abstract: A display device includes: a base layer including a display area including an emission area and a non-emission area adjacent to the emission area, and a non-display area around the display area; a light emitting element in the emission area on the base layer; a color filter layer located above the light emitting element; and a light blocking pattern on the light emitting element and including a first light blocking pattern in the non-emission area and a second light blocking pattern in the non-display area. The first light blocking pattern and the second light blocking pattern are different in thickness from each other.

Abstract: Disclosed is an electric hydraulic actuator including a hydraulic cylinder and the hydraulic power generator. The hydraulic cylinder includes a hollow rod that is connected to a piston and is linearly movable to protrude outward or to retract. The hydraulic power generator includes a motor, a fluid tank, and a gear pump and a pilot check valve disposed in a pump housing. The cylinder housing and the pump housing are directly coupled to each other. The cylinder housing includes a first port through which the working fluid is transferred to a first side of the piston and a second port connected to a return pipe that is provided in the hollow rod. The pump housing includes a third port that is configured to communicate with the first port and a fourth port that is configured to communicate with the second port.

Abstract: A high voltage switch circuit includes a first transistor, a first depletion mode transistor, a level shifter, a control signal generator, a second transistor and a second depletion mode transistor. The first transistor transmits the second driving voltage to an output terminal in response to a first gate signal. The first depletion mode transistor transmits the second driving voltage to the first transistor in response to feedback from the output terminal. The control signal generator generates first and second control signals in response to a level-shifted enable signal. The second transistor has a gate electrode connected to the first voltage and is turned on and off in response to the second control signal at a first end of the second transistor. The second depletion mode transistor is connected between a second end of the second transistor and the output terminal, and has a gate electrode receiving the first control signal.

Abstract: A high voltage switch circuit includes a first transistor, a first depletion mode transistor, a level shifter, a control signal generator, a second transistor and a second depletion mode transistor. The first transistor transmits the second driving voltage to an output terminal in response to a first gate signal. The first depletion mode transistor transmits the second driving voltage to the first transistor in response to feedback from the output terminal. The control signal generator generates first and second control signals in response to a level-shifted enable signal. The second transistor has a gate electrode connected to the first voltage and is turned on and off in response to the second control signal at a first end of the second transistor. The second depletion mode transistor is connected between a second end of the second transistor and the output terminal, and has a gate electrode receiving the first control signal.

Abstract: A method of operating a non-volatile memory includes; during power-on, reading control information from an information block and lock information from an additional information block, then upon determining that a secure block should be locked, generating a lock enable signal that inhibits access to data stored in the secure block, and a read-only enable signal that prevents change in the data stored in the additional information block.

Abstract: A method of operating a non-volatile memory includes; during power-on, reading control information from an information block and lock information from an additional information block, then upon determining that a secure block should be locked, generating a lock enable signal that inhibits access to data stored in the secure block, and a read-only enable signal that prevents change in the data stored in the additional information block.

Abstract: Multi-bit flash memory devices are provided. The multi-bit flash memory device includes an array of memory cells and a page buffer block including page buffers. Each of the page buffers has a single latch structure and performs a write operation with respect to memory cells according to loaded data. A buffer random access memory (RAM) is configured to store program data provided from an external host device during a multi-bit program operation. Control logic is provided that is configured to control the page buffer block and the buffer RAM so that program data stored in the buffer RAM is reloaded into the page buffer block whenever data programmed before the multi-bit program operation is compared with data to be currently programmed. The control logic is configured to store data to be programmed next in the buffer RAM before the multi-bit program operation is completed.

Abstract: Nonvolatile memory devices include a memory cell array having memory cells arranged in rows and columns, and an address storing unit that is configured to store therein an indicator of an initial column address and an indicator of an end column address, to identify a subset of the columns that extends from the initial column address to the end column address. A program circuit is configured to verify a programming operation for a selected row at the subset of the columns that extends from the initial column address to the end column address. Analogous methods of programming a nonvolatile memory device also may be provided.

Abstract: A multi-bit non-volatile memory device is provided. The memory device includes a memory cell array including a plurality of memory cells. A page buffer is electrically coupled to the memory cell array. The page buffer includes a plurality of latches configured to store a first bit of multi-bit data to be written into or read out from one of the plurality of memory cells of the memory cell array. A buffer random access memory (RAM) is electrically coupled to the page buffer. The buffer RAM is configured to store a second bit of the multi-bit data to be written into or read out from one of the plurality of memory cells of the memory cell array. Related systems, memory cards and methods are also provided.

Abstract: A flash memory includes memory cell array having memory cells divided into sectors, a page buffer block having groups of page buffers corresponding to the sectors, and a page buffer controller configured to control the groups of page buffers individually. In some embodiments, multiple groups of page buffers may be activated simultaneously to access multiple sectors, while page buffer groups for unselected sectors are deactivated.

Abstract: A flash memory device may include a memory cell array including a plurality of memory blocks and a partition information block, the partition information block storing partition information that indicates a boundary between multi-bit memory blocks and single-bit memory blocks among the memory blocks. The memory device may include a control logic configured to determining whether a memory block that a block address from the outside indicates has a multi-bit form or a single-bit form based on the partition information and to control program and read operations in a multi-bit form or a single-bit form based on a determination result. The control logic automatically programs data in the partition information block according to whether a fuse connected to the control logic fuse is cut or not, the data being used for preventing the partition information block from being programmed or erased.

Abstract: Multi-bit flash memory devices are provided. The multi-bit flash memory device includes an array of memory cells and a page buffer block including page buffers. Each of the page buffers has a single latch structure and performs a write operation with respect to memory cells according to loaded data. A buffer random access memory (RAM) is configured to store program data provided from an external host device during a multi-bit program operation. Control logic is provided that is configured to control the page buffer block and the buffer RAM so that program data stored in the buffer RAM is reloaded into the page buffer block whenever data programmed before the multi-bit program operation is compared with data to be currently programmed. The control logic is configured to store data to be programmed next in the buffer RAM before the multi-bit program operation is completed.

Abstract: A multi-bit non-volatile memory device is provided. The memory device includes a memory cell array including a plurality of memory cells. A page buffer is electrically coupled to the memory cell array. The page buffer includes a plurality of latches configured to store a first bit of multi-bit data to be written into or read out from one of the plurality of memory cells of the memory cell array. A buffer random access memory (RAM) is electrically coupled to the page buffer. The buffer RAM is configured to store a second bit of the multi-bit data to be written into or read out from one of the plurality of memory cells of the memory cell array. Related systems, memory cards and methods are also provided.

Abstract: A wordline decoder for a non-volatile memory device includes a first inverter to invert a block selection signal into a first inverted result on a first node, a second inverter to invert the signal on the first node into a second inverted result on a second node, a first and a second transistor, each coupled to a power supply, coupled in series between the second node and a third node, a third transistor coupled between the third node and a fourth node having a gate coupled to the third node, a fourth transistor coupled between a high voltage supply and a fifth node having a source coupled to the high voltage supply and a gate coupled to the third node, and a fifth transistor coupled between the fifth node and the third node having a gate coupled to the first node.

Abstract: A flash memory includes memory cell array having memory cells divided into sectors, a page buffer block having groups of page buffers corresponding to the sectors, and a page buffer controller configured to control the groups of page buffers individually. In some embodiments, multiple groups of page buffers may be activated simultaneously to access multiple sectors, while page buffer groups for unselected sectors are deactivated.

Abstract: A wordline decoder for a non-volatile memory device includes a first inverter to invert a block selection signal into a first inverted result on a first node, a second inverter to invert the signal on the first node into a second inverted result on a second node, a first and a second transistor, each coupled to a power supply, coupled in series between the second node and a third node, a third transistor coupled between the third node and a fourth node having a gate coupled to the third node, a fourth transistor coupled between a high voltage supply and a fifth node having a source coupled to the high voltage supply and a gate coupled to the third node, and a fifth transistor coupled between the fifth node and the third node having a gate coupled to the first node.

Abstract: Nonvolatile memory devices include a memory cell array having memory cells arranged in rows and columns, and an address storing unit that is configured to store therein an indicator of an initial column address and an indicator of an end column address, to identify a subset of the columns that extends from the initial column address to the end column address. A program circuit is configured to verify a programming operation for a selected row at the subset of the columns that extends from the initial column address to the end column address. Analogous methods of programming a nonvolatile memory device also may be provided.