Patents by Inventor Ho-Ku Lan

Ho-Ku Lan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9236429
    Abstract: A semiconductor structure includes a substrate, a dam element, a first isolation layer, a second isolation layer, and a conductive layer. The substrate has a conductive pad, a trench, a sidewall, a first surface, and a second surface opposite to the first surface. The conductive pad is located on the second surface. The trench has a first opening at the first surface, and has a second opening at the second surface. The dam element is located on the second surface and covers the second opening. The dam element has a concave portion that is at the second opening. The first isolation layer is located on a portion of the sidewall. The second isolation layer is located on the first surface and the sidewall that is not covered by the first isolation layer, such that an interface is formed between the first and second isolation layers.
    Type: Grant
    Filed: April 29, 2015
    Date of Patent: January 12, 2016
    Assignee: XINTEC INC.
    Inventors: Yu-Lin Yen, Sheng-Hao Chiang, Hung-Chang Chen, Ho-Ku Lan, Chen-Mei Fan
  • Publication number: 20150318348
    Abstract: A semiconductor structure includes a substrate, a dam element, a first isolation layer, a second isolation layer, and a conductive layer. The substrate has a conductive pad, a trench, a sidewall, a first surface, and a second surface opposite to the first surface. The conductive pad is located on the second surface. The trench has a first opening at the first surface, and has a second opening at the second surface. The dam element is located on the second surface and covers the second opening. The dam element has a concave portion that is at the second opening. The first isolation layer is located on a portion of the sidewall. The second isolation layer is located on the first surface and the sidewall that is not covered by the first isolation layer, such that an interface is formed between the first and second isolation layers.
    Type: Application
    Filed: April 29, 2015
    Publication date: November 5, 2015
    Inventors: Yu-Lin YEN, Sheng-Hao CHIANG, Hung-Chang CHEN, Ho-Ku LAN, Chen-Mei FAN
  • Publication number: 20060201848
    Abstract: In a container for transporting a reticle during a semiconductor manufacturing process, the reticle including a base made of isolating material and a metallic layer deposited onto a surface of the base, disclosed is a method for isolating and removing environmental contaminants which includes filling the container with inert gas, thereby purging the environmental contaminants, as well as inlet and outlet features to allow for the purging of clean inert gas and impurities.
    Type: Application
    Filed: March 14, 2005
    Publication date: September 14, 2006
    Inventors: Ting-Yu Lin, Yi-Ming Dai, Chi-Hung Liao, Li-Kong Turn, Louie Liu, Ho-Ku Lan, Hsiang Liu
  • Patent number: 6943124
    Abstract: A method is provided for forming features in a polyimide layer that is employed as an insulating layer or buffer layer during the fabrication of semiconductor devices or chip packaging structures. A pattern is formed in a photosensitive layer that has a high film retention after the development step and a crosslinked network that strengthens and stabilizes it for subsequent processing. The process involves exposing a negative tone photosensitive layer with a first exposure dose that is less than the normal dose used to image the material. The exposed layer is developed to provide a scum free substrate. A second exposure dose then strengthens the formed image by crosslinking unreacted components. First and second exposure doses are determined from a plot of film thickness loss vs. exposure energy. The method applies to photosensitive polyimide precursors as well as negative photoresists that are crosslinked by free radical or chemical amplification mechanisms.
    Type: Grant
    Filed: July 17, 2002
    Date of Patent: September 13, 2005
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Shin-Rung Lu, Ho-Ku Lan
  • Publication number: 20050191563
    Abstract: A method and system is disclosed for reducing and monitoring precipitated defects on mask reticles. A predetermined gas is provided into an environment surrounding the reticle assembly for reducing a formation of the precipitated defects around the mask reticle caused by photolithography under a light source having a small wavelength.
    Type: Application
    Filed: February 26, 2004
    Publication date: September 1, 2005
    Inventors: Yi-Ming Dai, Ting-Yu Lin, Ho-Ku Lan, Li-Kong Turn, Heng-Hsin Liu, Louie Liu, Tony Wu, Chi-Hung Liao
  • Patent number: 6021921
    Abstract: The present invention discloses a liquid dispensing system and a method for dispensing liquid that includes two hermetically sealed tanks each having a liquid container with a conduit pipe connecting the two containers. A differential pressure exists between the two tanks such that a process liquid can be fed from the second container into a dispensing nozzle under the differential pressure and the gravity of the liquid without the need of a pumping system. The problems of gel formation normally observed in conventional dispensing systems can be eliminated. A high viscosity, short shelf life liquid can be most suitably dispensed by the present invention novel dispensing system and method.
    Type: Grant
    Filed: October 27, 1997
    Date of Patent: February 8, 2000
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ho-Ku Lan, Chen-Cheng Kuo, Hung-Chih Chen, Shih-Shiung Chen
  • Patent number: 5989754
    Abstract: A photomask arrangement is disclosed to prevent the reticle patterns of a photomask from peeling caused by electrostatic discharge damage. The photomask includes: a substrate; a plurality of metal shielding layers formed on the surface of the substrate to provide the reticle patterns, wherein each two of the metal shielding layers are spaced apart by a clear scribe line; and a plurality of metal lines formed on the clear scribe line to connect the adjacent metal shielding layers, thereby increasing the effective surface area of the reticle patterns.
    Type: Grant
    Filed: September 5, 1997
    Date of Patent: November 23, 1999
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Shiung Chen, Ming-Fa Chen, Ho-Ku Lan, Ying-Chen Chao
  • Patent number: 5869219
    Abstract: The present invention discloses a method for coating a polyimide precursor on an electronic structure incorporating the use of a silicon coupling agent without any bubble defect in the film deposited. The method can be carried out by flowing at least one inert gas through a deposition chamber and thereby keeping the relative humidity in the chamber at below 25% to carry away the formation of any water molecules and water vapor to prevent the formation of bubbles in the film deposited.
    Type: Grant
    Filed: November 5, 1997
    Date of Patent: February 9, 1999
    Assignee: Taiwan Semiconductor Manufacturing Co. Ltd.
    Inventors: Chen-Cheng Kuo, Ho-Ku Lan, Hung-Chih Chen, Shih-Shiung Chen
  • Patent number: 5807787
    Abstract: A method is achieved for reducing the surface leakage current between adjacent bonding pads on integrated circuit substrates after forming a patterned polyimide passivation layer. When the polyimide layer is patterned to open contacts areas over the bonding pads, plasma ashing in oxygen is used to remove residual polyimide that otherwise causes high contact resistance, and poor chip yield. This plasma ashing also modifies the insulating layer between bonding pads resulting in an unwanted increase in surface leakage currents between bonding pads. The passivation process is improved by using a thermal treatment step in either a nitrogen or air ambient after the plasma ashing to essentially eliminate the increased surface leakage current and improve chip yield.
    Type: Grant
    Filed: December 2, 1996
    Date of Patent: September 15, 1998
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Jui Fu, Ho-Ku Lan, Ying-Chen Chao