Abstract: A method for manufacturing a criss-cross type X-ray grid may include: forming a plurality of criss-cross type grooves at predetermined intervals in a longitudinal direction and a lateral direction in a substrate made of an X-ray transparent material, through a semiconductor sawing machine, such that the grooves form a checker board shape as a whole; putting the substrate having the criss-cross type grooves formed therein into a storage tank filled with a molten X-ray absorbent material; filing the criss-cross type grooves, formed in the substrate, with the X-ray absorbent material by vacuuming the inside of the storage tank; and taking the substrate filled with the X-ray absorbent material out of the storage tank, and curing the substrate at room temperature.

Abstract: A method for manufacturing a criss-cross type X-ray grid may include: forming a plurality of criss-cross type grooves at predetermined intervals in a longitudinal direction and a lateral direction in a substrate made of an X-ray transparent material, through a semiconductor sawing machine, such that the grooves form a checker board shape as a whole; putting the substrate having the criss-cross type grooves formed therein into a storage tank filled with a molten X-ray absorbent material; filing the criss-cross type grooves, formed in the substrate, with the X-ray absorbent material by vacuuming the inside of the storage tank; and taking the substrate filled with the X-ray absorbent material out of the storage tank, and curing the substrate at room temperature.

Abstract: An SRAM cell includes a first PMOS pass transistor comprising a first gate electrode disposed on a first PMOS active region, a first NMOS pass transistor comprising a second gate electrode disposed on a first NMOS active region, a first PMOS pull-up transistor and a first NMOS pull-down transistor sharing a third gate electrode disposed on the first PMOS active region and the first NMOS active region and extending therebetween, a second PMOS pass transistor comprising a fourth gate electrode disposed on a second PMOS active region, a second NMOS pass transistor comprising a fifth gate electrode disposed on a second NMOS active region and a second pull-up transistor and a second pull-down transistor sharing a sixth gate electrode disposed on the second PMOS active region and the second NMOS active region and extending therebetween.

Abstract: An SRAM cell includes a first PMOS pass transistor comprising a first gate electrode disposed on a first PMOS active region, a first NMOS pass transistor comprising a second gate electrode disposed on a first NMOS active region, a first PMOS pull-up transistor and a first NMOS pull-down transistor sharing a third gate electrode disposed on the first PMOS active region and the first NMOS active region and extending therebetween, a second PMOS pass transistor comprising a fourth gate electrode disposed on a second PMOS active region, a second NMOS pass transistor comprising a fifth gate electrode disposed on a second NMOS active region and a second pull-up transistor and a second pull-down transistor sharing a sixth gate electrode disposed on the second PMOS active region and the second NMOS active region and extending therebetween.