Patents by Inventor Ho-Kwon Cha

Ho-Kwon Cha has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SRAM cells using shared gate electrode configuration
    Patent number: 8710592
    Abstract: An SRAM cell includes a first PMOS pass transistor comprising a first gate electrode disposed on a first PMOS active region, a first NMOS pass transistor comprising a second gate electrode disposed on a first NMOS active region, a first PMOS pull-up transistor and a first NMOS pull-down transistor sharing a third gate electrode disposed on the first PMOS active region and the first NMOS active region and extending therebetween, a second PMOS pass transistor comprising a fourth gate electrode disposed on a second PMOS active region, a second NMOS pass transistor comprising a fifth gate electrode disposed on a second NMOS active region and a second pull-up transistor and a second pull-down transistor sharing a sixth gate electrode disposed on the second PMOS active region and the second NMOS active region and extending therebetween.
    Type: Grant
    Filed: March 5, 2012
    Date of Patent: April 29, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sunme Lim, Hanbyung Park, Ho-Kwon Cha
  • SRAM CELLS USING SHARED GATE ELECTRODE CONFIGURATION
    Publication number: 20120228714
    Abstract: An SRAM cell includes a first PMOS pass transistor comprising a first gate electrode disposed on a first PMOS active region, a first NMOS pass transistor comprising a second gate electrode disposed on a first NMOS active region, a first PMOS pull-up transistor and a first NMOS pull-down transistor sharing a third gate electrode disposed on the first PMOS active region and the first NMOS active region and extending therebetween, a second PMOS pass transistor comprising a fourth gate electrode disposed on a second PMOS active region, a second NMOS pass transistor comprising a fifth gate electrode disposed on a second NMOS active region and a second pull-up transistor and a second pull-down transistor sharing a sixth gate electrode disposed on the second PMOS active region and the second NMOS active region and extending therebetween.
    Type: Application
    Filed: March 5, 2012
    Publication date: September 13, 2012
    Inventors: Sunme Lim, Hanbyung Park, Ho-Kwon Cha