Abstract: Gate drive circuit includes a plurality of stages connected one after another to each other. An m-th stage includes a pull-up section outputting a first clock signal as a gate signal of the m-th stage to an output terminal, a pull-down section applying a low voltage to the output terminal, a carry section outputting the first clock signal as a carry signal of the m-th stage in response to the high voltage of the first node signal, a first carry holding section maintaining the carry signal of the m-th stage at the low voltage in response to the high voltage of the first clock signal and a second carry holding section maintaining the carry signal of the m-th stage at the low voltage in response to a high voltage of the second clock signal.

Abstract: A method of driving a gate line includes: charging one of a scan start signal and a carry signal provided from a previous stage to a first node of a present stage; outputting a gate signal through a gate node of the present stage by pulling up a high level of a first clock signal at the first node to boost up a voltage potential of the first node; discharging the voltage potential of the first node and a voltage potential of the gate node to hold the first node and the gate node at a first power voltage as the first clock signal is shifted to a low level; and receiving a voltage potential signal of a second node of the previous stage, the second node holding a gate signal outputted from the previous stage, to reduce a ripple generated at the first node.

Abstract: A liquid crystal display device according to an exemplary embodiment includes: a first panel comprising a first portion and a second portion, wherein the first portion has a height lower than of the second portion; a second panel facing the first panel; a spacer disposed between the first panel and the second panel and contacting the first portion of the first panel; and a liquid crystal layer disposed between the first panel and the second panel.

Abstract: In the display apparatus, a gate driver receives at least one clock to sequentially provide gate lines in a display panel with a gate signal in a high state corresponding to a high interval of the clock. The gate driver includes a plurality of amorphous silicon transistors and is formed in the display panel through a thin film process. The clock has a delay time of about 2.0 ?s or less. If the delay time of the clock is reduced less than about 2.0 ?s, a threshold voltage margin of the transistors increases, so that the gate driver may not malfunction in a high temperature aging process. As a result, the gate driver may be prevented from malfunctioning in the high temperature aging process.

Abstract: A gate driver that comprises n shift registers, wherein n is an integer equal to or larger than 1, each of the n shift registers includes; a start stage which outputs a gate signal and starts its operation in response to a start signal, and a plurality of subsequent stages which are connected to each other in sequence, and which sequentially output a plurality of gate signals in response to a signal output from the start stage, wherein at least one stage of the plurality of subsequent stages is reset by the start signal.

Abstract: A display apparatus includes a storage line, a main-storage electrode branched from the storage line, and sub-storage electrodes branched from the main-storage electrode. The main-storage electrode and the sub-storage electrodes form storage capacitors with a pixel electrode. The main-storage electrode has a structure that is suitable for improving an aperture ratio of the display apparatus, and the sub-storage electrodes has a structure that is suitable for improving a driving capability of the display apparatus. Thus, a desired aperture ratio and a desired driving capability may be obtained by adjusting lengths of the main-storage electrode and the sub-storage electrodes.

Abstract: A first slit pattern is formed in a display substrate and a display panel of vertical alignment mode having the display substrate. The first slit pattern includes slits, a pair of projections and a pair of notches. A divergence point where the slits meet each other and an incision portion of the slits have the same function as the pair of projections in the generation of a singular point of liquid crystal. A contact hole exposing a part of an output electrode of a switching element is formed at a protective layer of an array substrate. A step recess is formed at a protective layer corresponding to a storage electrode, a divergence point of the slits is arranged to correspond to the storage electrode. The singular point of the liquid crystal is induced to occur at a regular position, and thus afterimages and spots can be prevented.

Abstract: Provided are a thin-film transistor (TFT) substrate and a display device having the same. In the TFT substrate and the display device having the same, first and second drain electrodes of first and second TFTs connected to first and second pixel electrodes, respectively, are vertically bent a plurality of times. The distance between each of the first and second source electrodes and the first or second drain electrode is maintained at a minimum interline gap to increase the distance between a data line and each of the first and second drain electrodes and minimize the length of a region of each of the first and second drain electrodes adjacent to the data line. Consequently, a coupling capacitance between the data line and each of the first and second drain electrodes can be reduced, and each unit pixel region can have a uniform parasite capacitance within a predetermined range. In addition, the luminance deviation of a display device, which performs inversion driving, can be reduced.

Abstract: A liquid crystal display including a liquid crystal display panel having a display area that displays an image in response to a gate signal and a data signal, and a peripheral area including first, second, third and fourth peripheral areas surrounding the display area; a plurality of gate drivers performing a scanning operating in response to a first control signal to output the gate signal, the gate drivers being arranged in the first peripheral area; a plurality of data drivers arranged in the second peripheral area adjacent to a gate driver that last performs the scanning operating among the gate drivers; and a signal transmission line connected to a gate driver that first performs the scanning operation among the gate drivers, and routed through the third and fourth peripheral areas opposite to the first and second peripheral areas, respectively, to provide the first control signal to the gate drivers.

Abstract: A thin film transistor for driving a gate line and a liquid crystal display having the same are provided. The thin film transistor for driving a gate line includes a gate electrode, a semiconductor layer formed on the gate electrode, a drain electrode formed on the semiconductor layer, a source electrode formed on the semiconductor layer and separated from the drain electrode and being coupled to the gate line, and a ripple-prevention electrode formed on the drain electrode which overlaps at least a part of the drain electrode.

Abstract: In a display apparatus, pixels are arranged in a matrix defined by gate lines and data lines, and each pixel includes a first sub pixel charged to a first pixel voltage and a second sub pixel charged to a second pixel voltage having a same voltage level as the first pixel voltage. A voltage controller controls a voltage level of the first and second pixel voltages charged in the pixels corresponding to the first through penultimate pixel rows in response to a next gate signal. A dummy voltage controller controls a voltage level of the first and second pixel voltages charged in the pixels corresponding to the last pixel row in response to a dummy gate signal. Where a dummy voltage controller is not included, a black matrix partially covers the efficient display area of the pixels corresponding to the last pixel row.

Abstract: A liquid crystal display device includes a first insulating substrate, a gate line and a data line which are formed on the first insulating substrate and intersect each other insulatedly to define a pixel area. A pixel electrode is electrically coupled to the data line and includes a first stem electrode which is parallel with the data line, a plurality of first branch electrodes which are connected with the first stem electrode and substantially parallel with each other, and a first edge electrode which is located at a connecting area between the first stem electrode and the first branch electrode and extends to an area between the first branch electrodes. A second insulating substrate is provided which includes a common electrode formed on the second insulating substrate, the common electrode including a plurality of second branch electrodes which are located between the first branch electrodes. The second branch electrodes are substantially parallel with the first branch electrodes.

Abstract: A liquid crystal display device according to an exemplary embodiment includes: a first panel comprising a first portion and a second portion, wherein the first portion has a height lower than of the second portion; a second panel facing the first panel; a spacer disposed between the first panel and the second panel and contacting the first portion of the first panel; and a liquid crystal layer disposed between the first panel and the second panel.