Abstract: A semiconductor chip may include: a body portion with a front surface and a rear surface; a pair of through electrodes penetrating the body portion; an insulating layer disposed over the rear surface of the body portion and the pair of through electrodes; and a rear connection electrode disposed over the insulating layer and connected simultaneously with the pair of through electrodes, wherein a distance between the pair of through electrodes is greater than twice a thickness of the insulating layer.

Abstract: A hot-plug controller of PCI (Peripheral Components Interconnects) bus using single chip is disclosed. A PCI hot-plug controller using FPGA and ASIC implements all functions necessary for the PCI hot-plug on a single chip, the PCI hot-plug controller includes: System Interface Unit transmitting data via PCI, USB and I2C bus; Register Unit, which is connected to the System Interface Unit, and receives reset control signal, Present Detection signal, Enable signal, LED control signal and physical ID signal from the outside, and stores the signals; Power Control Unit reading data from the Register Unit and outputting signal to control the system power and slot power; and Bus Isolation Unit reading the control signal from the Register Unit and making the signal-line between PCI bus signal and PCI slot ON/OFF.

Abstract: A diagnostic/control system using a multi-level I2C bus, includes: multiple I2C bus master devices (MD0 to MDn) connected to a primary I2C bus; a I2C bus multiplexer module, which separates multiple secondary I2C buses from said primary I2C bus, and which connects as many I2C bus slave devices (SD00 to SD0N, SD10 to SD1N, . . . , SDN1 to SDNN) are needed on said secondary I2C bus; and I2C bus slave devices (SD00 to SD0N, SD10 to SD1N, SDN1 to SDNN) connected to said secondary I2C bus. The I2C bus multiplexer module provides access at any instant between any I2C bus master device (MD0 to MDn) and any I2C bus slave device on the secondary I2C bus.

Abstract: A fault tolerant voltage regulator module (VRM) circuit for a processor simultaneously supplies a core voltage to a plurality of processors, has a plurality of main VRMs (VRM) for supplying the same core voltage to the plurality of processors, a stand-by VRM for use upon a fault occurring in the plurality of main VRMs, a plurality of diodes connected in parallel between each of the main VRMs and the stand-by VRM for automatically supplying power to the stand-by VRM, a plurality of first power islands for connecting each of the plurality of main VRMs to the processor and each of output port of the plurality of diodes, a control signal set switch for setting output voltage level of the stand-by VRM and a second power island for connecting the stand-by VRM to input ports of the plurality of diodes and the control signal set switch.