Patents by Inventor Ho-lin Wang

Ho-lin Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9471498
    Abstract: The present invention discloses a memory card access device, the control method thereof and a memory card access system. Said device comprises: a memory card interface circuit to generate card-read data according to a card-read signal or generate a card-writing signal according to card-writing data; a host interface circuit to generate host-read data according to a host-read signal or generate the host-writing signal according to host-writing data; and a control circuit, coupled to the memory card and host interface circuits respectively, operable to generate the host-writing data by processing the card-read data according to a predetermined cache protocol or generating the card-writing data by processing the host-read data according to the predetermined cache protocol, so as to treat a memory card as a cache device.
    Type: Grant
    Filed: May 5, 2014
    Date of Patent: October 18, 2016
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Chih-Ching Chien, Ho-Lin Wang
  • Publication number: 20150081951
    Abstract: The present invention discloses a memory card access device, the control method thereof and a memory card access system. Said device comprises: a memory card interface circuit to generate card-read data according to a card-read signal or generate a card-writing signal according to card-writing data; a host interface circuit to generate host-read data according to a host-read signal or generate the host-writing signal according to host-writing data; and a control circuit, coupled to the memory card and host interface circuits respectively, operable to generate the host-writing data by processing the card-read data according to a predetermined cache protocol or generating the card-writing data by processing the host-read data according to the predetermined cache protocol, so as to treat a memory card as a cache device.
    Type: Application
    Filed: May 5, 2014
    Publication date: March 19, 2015
    Inventors: CHIH-CHING CHIEN, HO-LIN WANG
  • Patent number: 7992077
    Abstract: A data slicer includes an error bit predictor, a DC level compensator, a co-channel detector, and an output device. The data slicer generates four bytes according to four slicing levels respectively. The four slicing levels are a DC level, a level generated by adding a predetermined offset to the DC level, a level generated by subtracting the predetermined offset from the DC level, and a compensated level generated by the DC level compensator. The co-channel detector determines if the compensated level has the co-channel interference. The output device generates an output byte according to indication signals generated by the co-channel detector and the error bit predictor and the parity check of the four bytes.
    Type: Grant
    Filed: November 22, 2007
    Date of Patent: August 2, 2011
    Assignee: NOVATEK Microelectronics Corp.
    Inventors: Chieh-Cheng Chen, Ho-Lin Wang, Ting Chiou
  • Patent number: 7688388
    Abstract: An image processing method and device thereof are provided. The device includes a capture device and a processor. The capture device is adopted for receiving a plurality of frames and comparing at least two adjacent frames to obtain an area selection signal according to a differential value there-between. The processor is connected to the capture device for receiving the area selection signal and to separate each of the adjacent frames into at least two areas. Each of the areas of the adjacent frames is performed by an image processing step respectively, and then the images of the areas are combined to obtain a resulted frame.
    Type: Grant
    Filed: August 8, 2005
    Date of Patent: March 30, 2010
    Assignee: Novatek Microelectronics Corp.
    Inventors: Tsui-Chin Chen, Dze-Chang Wang, Hsiao-Ming Huang, Chang-Lun Chen, Ho-lin Wang, Chui-Hsun Chiu
  • Publication number: 20090044087
    Abstract: A data slicer includes an error bit predictor, a DC level compensator, a co-channel detector, and an output device. The data slicer generates four bytes according to four slicing levels respectively. The four slicing levels are a DC level, a level generated by adding a predetermined offset to the DC level, a level generated by subtracting the predetermined offset from the DC level, and a compensated level generated by the DC level compensator. The co-channel detector determines if the compensated level has the co-channel interference. The output device generates an output byte according to indication signals generated by the co-channel detector and the error bit predictor and the parity check of the four bytes.
    Type: Application
    Filed: November 22, 2007
    Publication date: February 12, 2009
    Inventors: Chieh-Cheng Chen, Ho-Lin Wang, Ting Chiou
  • Publication number: 20060244823
    Abstract: An image processing method and device thereof are provided. The device includes a capture device and a processor. The capture device is adopted for receiving a plurality of frames and comparing at least two adjacent frames to obtain an area selection signal according to a differential value there-between. The processor is connected to the capture device for receiving the area selection signal and to separate each of the adjacent frames into at least two areas. Each of the areas of the adjacent frames is performed by an image processing step respectively, and then the images of the areas are combined to obtain a resulted frame.
    Type: Application
    Filed: August 8, 2005
    Publication date: November 2, 2006
    Inventors: Tsui-Chin Chen, Dze-Chang Wang, Hsiao-Ming Huang, Chang-Lun Chen, Ho-lin Wang, Chui-Hsun Chiu
  • Patent number: RE45306
    Abstract: An image processing method and device thereof are provided. The device includes a capture device and a processor. The capture device is adopted for receiving a plurality of frames and comparing at least two adjacent frames to obtain an area selection signal according to a differential value there-between. The processor is connected to the capture device for receiving the area selection signal and to separate each of the adjacent frames into at least two areas. Each of the areas of the adjacent frames is performed by an image processing step respectively, and then the images of the areas are combined to obtain a resulted frame.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: December 30, 2014
    Assignee: Novatek Microelectronics Corp.
    Inventors: Tsui-Chin Chen, Dze-Chang Wang, Hsiao-Ming Huang, Chang-Lun Chen, Ho-lin Wang, Chui-Hsun Chiu