Abstract: An apparatus comprising (i) a first circuit configured to generate one or more node signals at one or more internal nodes and (ii) a second circuit configured to present one or more of the node signals and a trigger signal in response to one or more control signals.

Abstract: An apparatus comprising a memory, a plurality of modules, an address translation unit and a controller. The memory may be arranged as a plurality of memory banks. Each of the plurality of modules may be configured to generate one or more addresses for accessing a particular one of the plurality of memory banks. The address translation unit may be configured to modify the one or more addresses in response to a control signal. The controller may be configured to generate the control signal in response to a computer executable instruction.

Abstract: Occurrence of uncorrectable errors in a stored sector of data which includes a data block, an error checking and correcting (ECC) block and an error detecting (CRC) block is detected. ECC logic is connected to a data bus and responsive to the ECC block in the sector, for generating an error polynomial identifying a location and a value for correctable errors in the sector. CRC logic is connected to the data bus and responsive to the CRC block in the sector for generating a syndrome identifying detected errors in the data block. An evaluation logic circuit is included that is coupled to the ECC logic and the CRC logic and responsive to the error polynomial and the syndrome for generating an uncorrectable error signal if the detected errors do not match the correctable errors. The error checking and correcting code is a Reed-Solomon code as in the X3B11 standard. Likewise the CRC code is a Reed-Solomon code as in the X3B11 standard.

Abstract: Occurrence of uncorrectable errors in a stored sector of data which includes a data block, an error checking and correcting (ECC) block and an error detecting (CRC) block is detected. ECC logic is connected to a data bus and responsive to the ECC block in the sector, for generating an error polynomial identifying a location and a value for correctable errors in the sector. CRC logic is connected to the data bus and responsive to the CRC block in the sector for generating a syndrome identifying detected errors in the data block. An evaluation logic circuit is included that is coupled to the ECC logic and the CRC logic and responsive to the error polynomial and the syndrome for generating an uncorrectable error signal if the detected errors do not match the correctable errors. The error checking and correcting code is a Reed-Solomon code as in the X3B11 standard. Likewise the CRC code is a Reed-Solomon code as in the X3B11 standard.

Abstract: An improved high speed two phase clock counter is disclosed. The counter includes a plurality of counter cells coupled to a transition pattern recognizer. Through the use of these elements a counter is provided that overcomes the power consumption and size limitation problems associated with known high speed counters.