Abstract: The present invention provides a method and apparatus for a new interleaver adaptation scheme that achieves “error free” and zero delay (interleaving—triangular) or near zero delay variation (interleaving—GCI), and with easier implementation but no additional memory required. The dummy insertion methods and systems embodiments of the invention provide an effective dummy byte insertion scheme for applications that require seamless on-line rate changes, e.g., SRA (seamless rate adaptation), DRR (dynamic rate repartitioning) and adaptive INP (impulse noise protection).

Abstract: The present invention provides a method and apparatus for a new interleaver adaptation scheme that achieves “error free” and zero delay (interleaving—triangular) or near zero delay variation (interleaving—GCI), and with easier implementation but no additional memory required. The dummy insertion methods and systems embodiments of the invention provide an effective dummy byte insertion scheme for applications that require seamless on-line rate changes, e.g., SRA (seamless rate adaptation), DRR (dynamic rate repartitioning) and adaptive INP (impulse noise protection).

Abstract: The present invention provides a method and apparatus for a new interleaver adaptation scheme that achieves “error free” and zero delay (interleaving—triangular) or near zero delay variation (interleaving—GCI), and with easier implementation but no additional memory required. The dummy insertion methods and systems embodiments of the invention provide an effective dummy byte insertion scheme for applications that require seamless on-line rate changes, e.g., SRA (seamless rate adaptation), DRR (dynamic rate repartitioning) and adaptive NP (impulse noise protection).

Abstract: The present invention provides a method and apparatus for a new interleaver adaptation scheme that achieves “error free” and zero delay (interleaving-triangular) or near zero delay variation (interleaving-GCI), and with easier implementation but no additional memory required. The dummy insertion methods and systems embodiments of the invention provide an effective dummy byte insertion scheme for applications that require seamless on-line rate changes, e.g., SRA (seamless rate adaptation), DRR (dynamic rate repartitioning) and adaptive INP (impulse noise protection).

Abstract: A method and apparatus for reducing noise correlation in a partial response channel through optimization of a look-ahead maximum likelihood (ML) detector. In the method of the present invention, the ML detector is optimized in light of the noise correlation generated by the partial response channel. The improved ML detector provides comparable performance to, or better performance than, a Viterbi detector in the presence of colored noise. In the present invention, a set of finite impulse response (FIR) transversal filters are used as the ML estimator for the look-ahead detector. The weighted sum outputs of the FIR filters are compared to a set of thresholds based on previously detected data to make the decision for current detection. The present invention improves the ML detector's performance and reduces its complexity by optimizing the coefficients of the FIR filters in the presence of the correlated or colored noise.