Abstract: A battery module includes at least one cell group, and a heat dissipating member coupled to one side of the at least one cell group to externally dissipate heat generated in the at least one cell group, wherein the at least one cell group includes at least one battery cell stack, a flame retardant cover coupled to the battery cell stack to encase both side surfaces and an upper portion of the battery cell stack, and a flame retardant member disposed between an upper surface of the battery cell stack and the flame retardant cover and formed of a porous material.

Abstract: A battery module includes at least one cell group, and a heat dissipating member coupled to one side of the at least one cell group to externally dissipate heat generated in the at least one cell group, wherein the at least one cell group includes at least one battery cell stack, a flame retardant cover coupled to the battery cell stack to encase both side surfaces and an upper portion of the battery cell stack, and a flame retardant member disposed between an upper surface of the battery cell stack and the flame retardant cover and formed of a porous material.

Abstract: A secondary battery includes a battery cell assembly in which a plurality of battery cells and one or more first insulating members are stacked; a second insulating member formed to cover at least a portion of one end of the battery cell assembly in a direction perpendicular to a stacking direction of the battery cells and the one or more first insulating members; an upper case located on the second insulating member; and a fire extinguishing member located between the second insulating member and the upper case.

Abstract: A gate in a semiconductor device is formed to have a dummy gate pattern that protects a gate. Metal lines are formed to supply power for a semiconductor device and transfer a signal. A semiconductor device includes a quad coupled receiver type input/output buffer. The semiconductor device is formed with a gate line that extends over an active region, and a gate pad located outside of the active region. The gate line and the gate pad are adjoined such that the gate line and a side of the gate pad form a line. Dummy gates may also be applied. The semiconductor device includes a first metal line patterns supplying power to a block having a plurality of cells, a second metal line pattern transferring a signal to the cells, and dummy metal line patterns divided into in a longitudinal direction.

Abstract: A gate in a semiconductor device is formed to have a dummy gate pattern that protects a gate. Metal lines are formed to supply power for a semiconductor device and transfer a signal. A semiconductor device includes a quad coupled receiver type input/output buffer. The semiconductor device is formed with a gate line that extends over an active region, and a gate pad located outside of the active region. The gate line and the gate pad are adjoined such that the gate line and a side of the gate pad form a line. Dummy gates may also be applied. The semiconductor device includes a first metal line patterns supplying power to a block having a plurality of cells, a second metal line pattern transferring a signal to the cells, and dummy metal line patterns divided into in a longitudinal direction.

Abstract: A gate in a semiconductor device is formed to have a dummy gate pattern that protects a gate. Metal lines are formed to supply power for a semiconductor device and transfer a signal. A semiconductor device includes a quad coupled receiver type input/output buffer. The semiconductor device is formed with a gate line that extends over an active region, and a gate pad located outside of the active region. The gate line and the gate pad are adjoined such that the gate line and a side of the gate pad form a line. Dummy gates may also be applied. The semiconductor device includes a first metal line patterns supplying power to a block having a plurality of cells, a second metal line pattern transferring a signal to the cells, and dummy metal line patterns divided into in a longitudinal direction.

Abstract: An integrated circuit memory interface device includes a debug controller for generating debug control signals in response to memory access control signals, and individual address and data boundary-scan registers. Each of the address and data boundary-scan registers has a predetermined number of cells which are daisy-chained from cell to cell. The address and data registers are placed between a memory device and a core logic which performs normal interface operations with respect to the devices during a normal mode. The interface device includes a test access port (TAP) controller which operates in synchronism with a test clock signal during test and debugging modes, and an instruction register. The TAP controller receives a test mode select signal and generates register control signals in response to the test clock and mode select signals.

Abstract: The present invention provides a test method of SOA (Single-Order Addressed) memory utilizing address data backgrounds applied to memory circuits. A memory test operation is performed using a total of (log.sub.2 N+1) address data backgrounds on an SOA memory having N mutually different addresses. Each address data background is written and read, then the inversion is written and read. Finally the address data background is again written and read for a total of 6 N(log.sub.2 N+1) operations.