Abstract: An apparatus for measuring round-trip time of a test signal using a programmable logic device comprises a pattern generator generating a test signal and measuring a round-trip time of the test signal, a programmable logic device of which internal circuits are configured to transmit the test signal in a predetermined manner, and bidirectional bus lines connecting the pattern generator and the programmable logic device. The round-trip time of the test signal is measured by a time difference between a starting time at which the pattern generator outputs the test signal and an arrival time at which the test signal is fed back to the pattern generator.

Abstract: An apparatus for measuring round-trip time of a test signal using a programmable logic device comprises a pattern generator generating a test signal and measuring a round-trip time of the test signal, a programmable logic device of which internal circuits are configured to transmit the test signal in a predetermined manner, and bidirectional buses connecting the pattern generator and the programmable logic device. The round-trip time of the test signal is measured by a time difference between a starting time at which the pattern generator outputs the test signal and an arrival time at which the test signal is fed back to the pattern generator.

Abstract: A system for test plural memories simultaneously includes a pattern generation part which generates a pattern signal for testing and transmits the signal to the memories, a delay part which receives data through a first data line from a first memory device that is disposed in a closest position from the delay part and a second data line from a second memory device that is disposed in a farthest position from the delay part, and a determination part which determines the result of testing by comparing the data from the first memory device and the second memory device. The delay part output the first data and the second data to the determination part simultaneously.

Abstract: An apparatus and method for acquiring data of fast fail memory includes a pattern generator for generating a pattern to be recorded to a device under test (DUT) and receiving DUT data from the DUT; a data transmitter for sending the DUT data and the pattern generated so as to correspond thereto to a failure analyzer from the pattern generator; and a failure analyzer for analyzing the DUT data and the pattern generated so as to correspond to the DUT data, which are received from the data transmitter, thus producing failure analysis information. The data transmitter (FIFO) able to advance the failure analysis time allows failure analysis to be performed before completion of testing, thereby shortening the total failure analysis time and overcoming hardware limitations for failure analysis.

Abstract: An apparatus and method for correcting an output signal of an FPGA-based memory test device includes a clock generator for outputting clock signals having different phases; and a pattern generator for outputting an address signal, a data signal and a clock signal in response to the clock signals input from the clock generator, and correcting a timing of each of the output signals using flip flops for timing measurement. Wherein the address signal, the data signal and the clock signal, through a pattern generator, are implemented with a programmable logic such as FPGA, thereby shortening the correcting time without the use of an external delay device, and increasing accuracy of output timing of the signal for memory testing, ultimately enhancing performance (accuracy) of a memory tester.

Abstract: An apparatus and method for acquiring data of fast fail memory includes a pattern generator for generating a pattern to be recorded to a device under test (DUT) and receiving DUT data from the DUT; a data transmitter for sending the DUT data and the pattern generated so as to correspond thereto to a failure analyzer from the pattern generator; and a failure analyzer for analyzing the DUT data and the pattern generated so as to correspond to the DUT data, which are received from the data transmitter, thus producing failure analysis information. The data transmitter (FIFO) able to advance the failure analysis time allows failure analysis to be performed before completion of testing, thereby shortening the total failure analysis time and overcoming hardware limitations for failure analysis.

Abstract: A system for simultaneously determining a memory test result includes a pattern generation part generating a pattern signal for testing so as to transmit the signal through an address line and a command line; a delay part receiving read data through a first data line from a closest memory device that is disposed closer to the system and to receive read data through a second data line from a farthest memory device that is disposed farther from the system; and a determination part simultaneously determining the read data of the closest memory device and the read data of the farthest memory device, which are simultaneously output from the delay part, using a determination clock, wherein the delay part recognizes the read data of the closest memory device and the read data of the farthest memory device.

Abstract: An apparatus and method for correcting an output signal of an FPGA-based memory test device includes a clock generator for outputting clock signals having different phases; and a pattern generator for outputting an address signal, a data signal and a clock signal in response to the clock signals input from the clock generator, and correcting a timing of each of the output signals using flip flops for timing measurement. Wherein the address signal, the data signal and the clock signal, through a pattern generator, are implemented with a programmable logic such as FPGA, thereby shortening the correcting time without the use of an external delay device, and increasing accuracy of output timing of the signal for memory testing, ultimately enhancing performance (accuracy) of a memory tester.

Abstract: A device for calculating round-trip time of a memory test using a programmable logic includes a pattern generation part including two pairs of input/output (IO) pins to generate a pattern signal for testing, and receiving a feedback signal through bidirectional buses from IO lines; two pairs of bidirectional buses for relaying a signal between the pattern generation part and a programmable logic part; and a programmable logic part for transmitting the pattern signal to the IO lines through the bidirectional buses and transmitting the feedback signal to the bidirectional buses from the IO lines, and including a multiplexer for crossing a signal connection direction upon calculation of the feedback signal, wherein the pattern generation part measures an input time of the feedback signal based on an output time of the pattern signal, thus calculating the round-trip time of the signal.