Patents by Inventor Ho Seng

Ho Seng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060084240
    Abstract: Methods for forming an edge contact on a die and edge contact structures are described. The edge contacts on the die do not increase the height of the die. The edge contacts are positioned on the periphery of a die. The edge contacts are positioned in the saw streets. Each edge contact is connected to one bond pad of each die adjacent the saw street. The edge contact is divided into contacts for each adjacent die when the dies are separated. In an embodiment, a recess is formed in the saw street. In an embodiment, the recess is formed by scribing the saw street with a mechanical cutter. The recess is patterned and contact material is deposited to form the edge contacts.
    Type: Application
    Filed: November 17, 2005
    Publication date: April 20, 2006
    Inventors: Chia Poo, Boon Jeung, Low Waf, Chan Yu, Neo Loo, Eng Koon, Ser Leng, Chua Kwang, So Chung, Ho Seng
  • Publication number: 20050268763
    Abstract: Improperly mounted wafer saw blades can damage wafers cut or diced with the blades. Embodiments of this invention employ sensors to measure a distance to the blade to help indicate if the blade is improperly mounted. In one method of the invention, a the distance to the blade face is measured as the blade is rotated and a variance in this measured distance is determined. If the variance is no greater than a predetermined maximum, the blade may be used to cut the wafer. In one apparatus of the invention, a wafer saw include a blade and a sensor. The sensor is adapted to monitor a distance to a face of the rotating blade. A processor coupled to the sensor may indicate if the distance to the face of the blade as it rotates deviates too far from a baseline position of the blade face.
    Type: Application
    Filed: July 28, 2005
    Publication date: December 8, 2005
    Inventors: Neo Peng, Tan Chuan, Ho Seng, Chew Chye, Lim Har, Tan Chua
  • Publication number: 20050029668
    Abstract: Methods for forming an edge contact on a die and edge contact structures are described. The edge contacts on the die do not increase the height of the die. The edge contacts are positioned on the periphery of a die. The edge contacts are positioned in the saw streets. Each edge contact is connected to one bond pad of each die adjacent the saw street. The edge contact is divided into contacts for each adjacent die when the dies are separated. In an embodiment, a recess is formed in the saw street. In an embodiment, the recess is formed by scribing the saw street with a mechanical cutter. The recess is patterned and contact material is deposited to form the edge contacts.
    Type: Application
    Filed: August 30, 2004
    Publication date: February 10, 2005
    Inventors: Chia Poo, Boon Jeung, Low Waf, Chan Yu, Neo Loo, Eng Koon, Ser Leng, Chua Kwang, So Chung, Ho Seng
  • Patent number: 6157331
    Abstract: In the present invention is described a forward feed sigma delta modulator of higher order having automatic saturation detection and recovery. The modulator is separated into two parts which are connected together when there is no saturation, and disconnected when saturation is detected and recovery takes place. The first part contains an integrator and input output circuitry to allow continuous operation of the modulator. The second part contains additional integrators to provider for a higher order modulator and the saturation detector. The modulator can be constructed of single ended or differential switched capacitor technology, and there is a digital saturation detection scheme.
    Type: Grant
    Filed: October 1, 1998
    Date of Patent: December 5, 2000
    Assignee: Tritech Microelectronics, Ltd.
    Inventors: Liusheng Liu, David Ho Seng Poh
  • Patent number: 6066537
    Abstract: A multilevel capacitor structure compatible with CMOS processing for use in switched capacitor circuits is disclosed. The capacitor structure has an associated parasitic capacitor which is placed in such a way so as to minimize the impact on the performance of a the switched capacitor circuit. The parasitic capacitor is formed between a first plate of the shielded capacitor and a diffusion well within a substrate. The diffusion well is connected to a quiet voltage reference source to isolate the shielded capacitor from noise present on the substrate. The shielded capacitor has a first plate that is fabricated from a first conductive material such as polycrystalline silicon or polycide, a second plate fabricated from a second conductive material such as a first level of metal on an integrated circuit, and a third capacitor plate fabricated from a second level of metal of an integrated circuit.
    Type: Grant
    Filed: February 2, 1998
    Date of Patent: May 23, 2000
    Assignee: Tritech Microelectronics, Ltd.
    Inventor: David Ho Seng Poh