Abstract: A method and an apparatus for verifying a logic circuit, capable of quicker operation, being applied to a logic gate-level or transistor-level circuit design, and verifying timing and analog signal characteristics of a signal. The logic circuit verification method includes a wave file generation stage and a logic circuit verification stage. The wave file generation stage generates a wave file that includes the waveforms of all nodes of the logic circuit using a design source file of the logic circuit. The stage of verification of the logic circuit verifies the logic circuit using a design reference file, which includes ideal operations of all the nodes of the logic circuit, and the wave file.

Abstract: A method and an apparatus for verifying a logic circuit, capable of quicker operation, being applied to a logic gate-level or transistor-level circuit design, and verifying timing and analog signal characteristics of a signal. The logic circuit verification method includes a wave file generation stage and a logic circuit verification stage. The wave file generation stage generates a wave file that includes the waveforms of all nodes of the logic circuit using a design source file of the logic circuit. The stage of verification of the logic circuit verifies the logic circuit using a design reference file, which includes ideal operations of all the nodes of the logic circuit, and the wave file.