Patents by Inventor Ho-sun Chung

Ho-sun Chung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5745655
    Abstract: A mapping circuit includes a linear circuit for outputting a signal which is linearly changed with respect to its input, a non-linear circuit for outputting a signal which is non-linearly changed with respect to its input, and an adder for summing the output signals of the linear and non-linear circuits and an external input signal. A chaotic neuron circuit using the mapping circuit has a simple structure and more precise chaos characteristics. A chaotic neural network can thus be formed by the serial and/or parallel interconnection of a plurality of chaotic neuron circuits, wherein the weight of each neuron is controlled.
    Type: Grant
    Filed: January 19, 1995
    Date of Patent: April 28, 1998
    Assignee: Gold Star Electron Co., Ltd.
    Inventors: Ho-sun Chung, Ik-soo Lee
  • Patent number: 5613042
    Abstract: A chaotic recurrent neural network includes N chaotic neural networks for receiving an external input and the outputs of N-1 chaotic neural networks among said N chaotic neural networks and performing an operation according to the following dynamic equation ##EQU1## wherein W.sub.ij is a synapse connection coefficient of the feedback input from the "j"th neuron to the "i"th neuron, X.sub.i (t) is the output of the "i"th neuron at time t, and .gamma..sub.i, .alpha. and and k are a time-delaying constant, a non-negative parameter and a refractory time attenuation constant, respectively, and wherein Z.sub.i (t) represents X.sub.i (t) when i belongs to the neuron group I and represents a.sub.i (t) when i belongs to the external input group E. Also, a learning algorithm for the chaotic recurrent neural network increases its learning efficiency.
    Type: Grant
    Filed: January 27, 1995
    Date of Patent: March 18, 1997
    Assignee: Gold Star Electron Co., Ltd.
    Inventors: Ho-sun Chung, Hye-young Tak
  • Patent number: 5517139
    Abstract: A non-linear circuit includes a first variable resistor one end of which is applied with an input signal, an amplifier whose inverting input is connected to the other end of the first variable resistor and whose non-inverting input is connected to ground, a second variable resistor one end of which is connected to the inverting input of the amplifier, a third variable resistor one end of which is connected to the output of the amplifier and the other end being connected to the other end of the second variable resistor, and a fourth variable resistor one end of which is applied with the input signal and the other end being connected to the third variable resistor.
    Type: Grant
    Filed: February 1, 1995
    Date of Patent: May 14, 1996
    Assignee: Gold Star Electron Co., Ltd.
    Inventors: Ho-sun Chung, Yil-suk Yang
  • Patent number: 5471557
    Abstract: A speech recognition system for recognizing the remote-controlling vocal commands of TV sets and VCRs comprises a microphone for receiving the speech pronounced by a user; a speech analyzer for analyzing the speech input via the microphone; circuitry for detecting a vocal section of the speech from the speech analyzer and performing a time-axis normalization and a binarization for the detected vocal section; and a multilayer neural network for receiving the binarization data from the aforementioned circuitry and then performing the learning, to thereby output the speech recognition result. Accordingly, the present invention can enhance the recognition ratio of speech.
    Type: Grant
    Filed: August 26, 1993
    Date of Patent: November 28, 1995
    Assignee: Gold Star Electron Co., Ltd.
    Inventors: Ho-sun Chung, Soo-yong Lee
  • Patent number: 5450528
    Abstract: A self-learning multi layer neural network and the learning method thereof are characterized in that N-bit input data and M-bit desired output data are received, a weight value of each synapse is adjusted so as to produce output data corresponding to the input data, and self-learning is performed while proceeding to a next layer. Thus, it is not necessary for the user to input and adjust all the weight values of the respective synapse while the network performs self-learning and a desired function.
    Type: Grant
    Filed: January 19, 1995
    Date of Patent: September 12, 1995
    Assignee: Gold Star Electron Co., Ltd.
    Inventors: Ho-sun Chung, Kyung-hun Lee
  • Patent number: 5448682
    Abstract: A programmable multilayer neural network includes a weight storing circuit for storing the weight of each synapse to perform an intended function, an interfacing circuit for transmitting the weight value stored in the storing circuit to each synapse, and a multilayer neural network circuit programmed to have the weight from the weight storing circuit and for outputting an intended output.
    Type: Grant
    Filed: January 17, 1995
    Date of Patent: September 5, 1995
    Assignee: Gold Star Electron Co., Ltd.
    Inventors: Ho-sun Chung, Kyung-hun Lee
  • Patent number: 5442209
    Abstract: A synapse MOS transistor has gate electrodes of different lengths, different widths or different lengths and widths, between one source region and one drain region. Thus, when using the synapse MOS transistor to implement a neural network, the chip area can be greatly reduced.
    Type: Grant
    Filed: June 2, 1994
    Date of Patent: August 15, 1995
    Assignee: Gold Star Electron Co., Ltd.
    Inventor: Ho-sun Chung
  • Patent number: 5347613
    Abstract: Disclosed is a multi-layer neural network and circuit design method.
    Type: Grant
    Filed: August 15, 1991
    Date of Patent: September 13, 1994
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ho-sun Chung, Hyo-jin Han
  • Patent number: 5293458
    Abstract: Disclosed is a multi-layer neural network and circuit design method.
    Type: Grant
    Filed: August 15, 1991
    Date of Patent: March 8, 1994
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ho-sun Chung, Sin-jin Kim
  • Patent number: 5260706
    Abstract: A priority encoder using a MOS array and neural network concepts is composed of an input side neuron group, an output side neuron group, a synapse group, a bias group and inverters. The encoder is simple in its construction and fast in its operating speed compared with the conventional priority encoders utilizing simple Boolean logic.
    Type: Grant
    Filed: April 3, 1992
    Date of Patent: November 9, 1993
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Ho-sun Chung
  • Patent number: 5239597
    Abstract: A conversion circuit of binary dither image to multilevel image comprises a counter utilizing concepts of a neural network, an 8 bit register and 8 OR gates, resulting in high speed of operation. The counter uses a neural network based on the Hopfield model and is made up of an input synapse group, a first bias synapse group, a feedback synapse group, a second bias synapse group, a neuron group and an invertor group.
    Type: Grant
    Filed: February 25, 1991
    Date of Patent: August 24, 1993
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ho-sun Chung, Ji-hwan Yeo
  • Patent number: 5177746
    Abstract: An error correction circuit is provided which uses NMOS and PMOS synapses to form neural network type responses to a coded multi-bit input. Use of MOS technology logic in error correction circuits allows such devices to be easily interfaced with other like technology circuits without the need to use distinct interface logic as with conventional error correction circuitry.
    Type: Grant
    Filed: July 9, 1990
    Date of Patent: January 5, 1993
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Ho-sun Chung
  • Patent number: 5166938
    Abstract: An error correction circuit is provided which uses NMOS and PMOS synapses to form network type responses to a coded multi-bit input. Use of MOS technology logic in error correction circuits allows such devices to be easily interfaced with other like technology circuits without the need to use distinct interface logic as with conventional error correction circuitry.
    Type: Grant
    Filed: July 9, 1990
    Date of Patent: November 24, 1992
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Ho-Sun Chung
  • Patent number: 5155699
    Abstract: A divider using neural network configurations comprises a subtractor, a selecting means, a first latch means, a second latch means, a shift register and a control means. The subtractor of the divider comprises plural inverters and plural 3-bit full-adders which are composed of four output lines, an input synapse group, a first bias synapse group, a second bias synapse group, a feedback synapse group, a neuron group and an inverter group.
    Type: Grant
    Filed: July 10, 1990
    Date of Patent: October 13, 1992
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ho-sun Chung, Sin-jin Kim, Tae-hun Kim
  • Patent number: 5130944
    Abstract: A divider circuit for efficiently and quickly performing a hardware implemented division by adopting a neural network architecture. The circuit includes a series of cascaded subtracter components that complement the divisor input and effectively perform an adder function. The subtracters include a synaptic configuration consisting of PMOS transistors, NMOS transistors, and CMOS inverters. The components are arranged in accordance with the predetermined connection strength assigned to each of the transistors and its respective position in the neural type network arrangement.
    Type: Grant
    Filed: July 9, 1990
    Date of Patent: July 14, 1992
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ho-sun Chung, Sin-jin Kim, Tae-hun Kim
  • Patent number: 5086405
    Abstract: A floating point adder circuit using neural network concepts and having high speed operation is obtained by a controlling circuit using a comparator and an operating circuit using an adder and a subtractor.
    Type: Grant
    Filed: July 10, 1990
    Date of Patent: February 4, 1992
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ho-sun Chung, Seung-yeob Paek